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Technical Committee on VLSI Design Technologies (VLD)
Chair: Toshiyuki Shibuya (Fujitsu Labs.) Vice Chair: Yusuke Matsunaga (Kyushu Univ.)
Secretary: Noriyuki Minegishi (Mitsubishi Electric), Hiroyuki Tomiyama (Ritsumeikan Univ.)
Assistant: Takehiro Miyazawa (MMS), Ryo Yamamoto (Mitsubishi Electric)

DATE:
Mon, Mar 2, 2015 13:00 - 16:35
Tue, Mar 3, 2015 08:50 - 16:40
Wed, Mar 4, 2015 08:50 - 14:40

PLACE:

TOPICS:

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Mon, Mar 2 PM (13:00 - 14:40)
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(1) 13:00 - 13:25
A Fast Lithographic Mask Correction Algorithm
Ahmd Awad, Atsushi Takahashi (Tokyo Institute of Technology)

(2) 13:25 - 13:50
A cut-pattern reduction method for routing in Self-Aligned Double Patterning
Noriyuki Takahashi, Takeshi Ihara, Atsushi Takahashi (Tokyo Tech)

(3) 13:50 - 14:15
Faster Numberlink solution using possibilities of topological routing
Yuichiro Tanaka, Atsushi Takahashi (Tokyo Tech)

(4) 14:15 - 14:40
Zero-weighted Cycle Finding Method for Exchanging Pin Pair on Set-Pair Rouitng
Yuta Nakatani, Atsushi Takahashi (Tokyo Tech)

----- Break ( 15 min. ) -----

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Mon, Mar 2 PM (14:55 - 16:35)
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(5) 14:55 - 15:20
Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming
Masato Ito, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)

(6) 15:20 - 15:45
Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)

(7) 15:45 - 16:10
Studies on Representation of Stacked Rectangular Dissections for 3D-LSI Floorplan
Kazufumi Kogai, Kunihiro Fujiyoshi (TUAT)

(8) 16:10 - 16:35
A High Stability and Low Leakage Current Six-Transistor CMOS SRAM Employing a Single Low Supply Voltage
Nobuaki Kobayashi, Ryusuke Ito, Koji Motojima, Tadayoshi Enomoto (Chuo Univ.)

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Tue, Mar 3 AM (08:50 - 10:05)
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(9) 08:50 - 09:15
A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture
Song Bian, Michihiro Shintani (Kyoto Univ.), Zheng Wang (RWTH Aachen Univ.), Masayuki Hiromoto (Kyoto Univ.), Anupam Chattopadhyay (Nanyang Tech. Univ.), Takashi Sato (Kyoto Univ.)

(10) 09:15 - 09:40
A low-power soft error tolerant latch scheme
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)

(11) 09:40 - 10:05
Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI
Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)

----- Break ( 15 min. ) -----

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Tue, Mar 3 AM (10:20 - 12:00)
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(12) 10:20 - 10:45
ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths
Junghoon Oh, Mineo Kaneko (JAIST)

(13) 10:45 - 11:10
Generation of Asynchronous Circuits from a High-level Synthesis Tool
Taichi Komine, Hiroshi Saito (University of Aizu)

(14) 11:10 - 11:35
A design of FIR filters using High Level Synthesis
-- A automated design of FIR filters --
Ryo Yamamoto, Naoya Okada, Noriyuki Minegishi (MELCO)

(15) 11:35 - 12:00
A Virtual/Real Combined Verification Method for FPGAs
Yoshimasa Ishino (MMS)

----- Lunch Break ( 80 min. ) -----

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Tue, Mar 3 PM (13:20 - 14:20)
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(16) 13:20 - 14:20
[Invited Talk]
Research in Industry and University for VLSI Design
Satoshi Goto (Waseda Univ.)

----- Break ( 15 min. ) -----

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Tue, Mar 3 PM (14:35 - 16:40)
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(17) 14:35 - 15:00
[Memorial Lecture]
Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.)

(18) 15:00 - 15:25
[Memorial Lecture]
A Performance Enhanced Dual-switch Network-on-Chip Architecture
Lian Zeng, Takahiro Watanabe (Waseda Univ.)

(19) 15:25 - 15:50
[Memorial Lecture]
A Length Matching Routing Method for Disordered Pins in PCB Design
Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ.)

(20) 15:50 - 16:15
[Memorial Lecture]
Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.)

(21) 16:15 - 16:40
[Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

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Wed, Mar 4 AM (08:50 - 10:05)
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(22) 08:50 - 09:15
Physical Unclonable Function Using RTN-Induced Time-Dependent Frequency Variance in Ring Oscillator
Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)

(23) 09:15 - 09:40
On PLL Layouts Evaluation based on Transistor-array Style
Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)

(24) 09:40 - 10:05
Ground Bounce Suppressive Effect using Power Switch Driver to control Power Switch Rise Time
Tetsutaro Ohnishi, Kimiyoshi Usami (S.I.T.)

----- Break ( 15 min. ) -----

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Wed, Mar 4 AM (10:20 - 12:00)
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(25) 10:20 - 10:45
Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design
Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo)

(26) 10:45 - 11:10
LSI implementation of FEC for high-speed optical communication
Koji Miyanohana, Susumu Hirano, Hideo Yoshida, Yoshikuni Miyata, Kenya Sugihara, Kazuo Kubo, Yoshiaki Konishi, Kiyoshi Onohara, Noriyuki Minegishi, Takashi Sugihara (Mitsubishi Elec.)

(27) 11:10 - 11:35
Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide
Jun Kawasaki, Kimiyoshi Usami (S.I.T.)

(28) 11:35 - 12:00
A parallel Algorithm for Realizing the Lax-Friedrichs Scheme in Computational Fluid Dynamics and its FPGA Implementation
Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.)

----- Lunch Break ( 60 min. ) -----

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Wed, Mar 4 PM (13:00 - 14:40)
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(29) 13:00 - 13:25
An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework
Satoshi Ohtsuki, Atsushi Takahashi (Tokyo Tech)

(30) 13:25 - 13:50
A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

(31) 13:50 - 14:15
Implementation and evaluation of architecture using lookup table for approximate computing
Shoichiro Sugiyama, tanvir ahmed, Yuko Hara-Azumi (Titech)

(32) 14:15 - 14:40
List-scheduling for tasks with execution time variation
Komei Nomura, Yasuhiro Takashima (Univ. of Kitakyushu)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Mon, May 11, 2015 - Wed, May 13, 2015: Kitakyushu International Conference Center , Topics: LSI and System Workshop 2015
Thu, May 14, 2015: Kitakyushu International Conference Center [Wed, Mar 11], Topics: System Design, etc.
Wed, Jun 17, 2015 - Thu, Jun 18, 2015: Otaru University of Commerce [Thu, Apr 16], Topics: System, signal processing and related topics

# SECRETARY:
Noriyuki Minegishi (Mitsubishi Electric Corporation)
E-mail: