ken-system: Advance Program - 2007-12-ICD-ITE-CE

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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Akira Matsuzawa (Tokyo Inst. of Tech.) Vice Chair: Kunio Uchiyama (Hitachi)
Secretary: Yoshiharu Aimoto (NECEL), Makoto Nagata (Kobe Univ.)
Assistant: Minoru Fujishima (Univ. of Tokyo), Yoshio Hirose (Fujitsu Labs.)

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Technical Group on Consumer Electronics (ITE-CE)
Chair: Takuya Imaide
Secretary: Tkayoshi Yamaguchi (Sharp), Kiyohiko Ishikawa, Hideaki Miyahara

DATE:
Thu, Dec 13, 2007 13:00 - 17:40
Fri, Dec 14, 2007 09:15 - 15:05

PLACE:
(Prof Michiaki Muraoka)

TOPICS:

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Thu, Dec 13 PM (13:00 - 13:50)
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(1) 13:00 - 13:50
[Invited Talk]
An LSI Design of Frame Rate Conversion Technology for LCD-TV
Akihisa Yamada (Sharp)

----- Break ( 15 min. ) -----

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Thu, Dec 13 PM (14:05 - 16:10)
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(2) 14:05 - 14:30
Current Mode Transceiver at 625Mbps, 3mW in 1.5V for Mobile Applecations
Tetsuhiro Ogino, Takefumi Yoshikawa, Makoto Nagata (Kobe Univ.)

(3) 14:30 - 14:55
A 1.8 mm2, 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique
Tomohiro Sano, Takaya Maruyama, Ikuo Yasui, Hisayasu Sato, Toshihiko Shimizu (Renesas technology Corp.)

(4) 14:55 - 15:20
A 2.4GHz ISM-band digital CMOS wireless transceiver with an intra-symbol adaptively intermittent Rx.
Haruya Ishizaki, Koichi Nose, Masayuki Mizuno (NEC)

(5) 15:20 - 15:45
Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization
Hiroshi Kodama, Hiroyuki Okada, Kiyoshi Yanagisawa, Hiromu Ishikawa, Akio Tanaka (NEC)

(6) 15:45 - 16:10
Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Application
Takashi Kawamoto (Hitachi), Takayuki Noto, Hiromitsu Inada, Tomoaki Takahashi (Renesas)

----- Break ( 15 min. ) -----

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Thu, Dec 13 PM (16:25 - 17:40)
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(7) 16:25 - 16:50
A new SRAM memory cell with small cell ratio using dynamic stability
Yuji Kihara (Renesas Technology), Yutaka Arita (Fujita Health University Collage), Leona Okamura (Waseda University Graduated School), Hirotoshi Sato (Renesas Technology), Tsutomu Yoshihara (Waseda University Graduated School)

(8) 16:50 - 17:15
A Low Dynamic Power and Low Leakage Power 90-nm CMOS SRAM with Wide Operating Margin
Takeshi Iwanari, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)

(9) 17:15 - 17:40
A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing
Yuichiro Murachi, Junichi Miyakoshi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)

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Fri, Dec 14 AM (09:15 - 10:05)
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(10) 09:15 - 09:40
A Study on Mutual Data Transfer Control Circuits for Self-Timed Web-Pipeline
Kazuhiro Komatsu, Shuji Sannomiya, Makoto Iwata (Kochi Univ. of Tech.), Suguru Kameda, Kazuo Tsubouchi (Tohoku Univ.)

(11) 09:40 - 10:05
Digital Signal Processing for Motor Driving with Delta-Sigma Modulated ADC
Yasunori Kobori, Tatsuya Furuya, Yoshihisa Yamada, Tomoharu Sato, Tetsuya Taura, Ibuki Mori, Masashi Kono, Kazuyuki Kobayashi, Haruo Kobayashi (Gunma Univ.), Yasuhiko Kokami, Hiroshi Kuroiwa, Minoru Kurosawa (Renesas)

----- Break ( 15 min. ) -----

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Fri, Dec 14 (10:20 - 12:00)
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(12) 10:20 - 10:45
A VGA 30-fps Real-Time Optical-Flow Processor Core for Moving Picture Recognition
Hajime Ishihara, Masayuki Miyama (Kanazawa Univ.), Yuichiro Murachi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.), Yoshio Matsuda (Kanazawa Univ.)

(13) 10:45 - 11:10
Four-Pixel accuracy Motion Estimation Unit using Bit-Truncation for Multiple Extended Templates
Tomotaka Katano, Saburo Jhonen, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ)

(14) 11:10 - 11:35
Human Extraction Algorithm Using Shape Features and Its Processor Architecture
Shota Hashimoto, Akio Sasaki, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)

(15) 11:35 - 12:00
A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama (Tohoku Univ.)

----- Lunch Break ( 60 min. ) -----

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Fri, Dec 14 (13:00 - 15:05)
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(16) 13:00 - 13:50
[Invited Talk]
Recent Trend of Transmission Technology for Super Resolution Images
Sei Naito, Shigeyuki Sakazawa, Atsushi Koike (KDDI R&D Labs.)

(17) 13:50 - 14:15
A Low Power and High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications
Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe (Renesas Technology Corp.)

(18) 14:15 - 14:40
Versatile Media Processor for Super High Definition (VMP/SHD)
-- The scalable architecture of parallel overlay frame engine --
Kenji Toda, Toshihiro Katashita, Yohei Hori, Osamu Morikawa (AIST)

(19) 14:40 - 15:05
A multi matrix-processor core architecture for real-time image processing SoC
Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas)

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, Jan 17, 2008 - Fri, Jan 18, 2008: Kikai-Shinko-Kaikan Bldg [Wed, Nov 14]
Wed, Mar 5, 2008 - Fri, Mar 7, 2008: TiRuRu [Wed, Dec 12], Topics: System-on-silicon design techniques and related VLSs

# SECRETARY:
Yoshio Hirose (Fujitsu Laboratories Ltd.)
TEL +81-44-754-2783, +81-44-754-2744
E-mail:y