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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Nagisa Ishiura (Kwansei Gakuin Univ.) Vice Chair: Kazutoshi Wakabayashi (NEC) Secretary: Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Hidetoshi Onodera (Kyoto Univ.) Secretary: Isaro Utsumi (OKI Network LSI), Tohru Ishihara (Kyushu Univ.), Yutaka Tamiya (Fujitsu Lab.) DATE: Thu, May 8, 2008 13:30 - 17:05 Fri, May 9, 2008 10:00 - 15:25 PLACE: Kobe University Centennial Hall Room A(Rokkoudai-cho, 1-1, Nada-ku, Kobe, 657-8501. http://neweb.h.kobe-u.ac.jp/epg/sdkk/sdkk.html. Kobe Univ. Innovative Software and Silicon Architecture Lab. Prof. Hiroshi Kawaguchi. 078-803-6317) TOPICS: System Design, etc. ---------------------------------------- Thu, May 8 PM (13:30 - 14:30) ---------------------------------------- (1) 13:30 - 14:30 [Invited Talk] HW/SW Co-verification Method Using FPGAs Yuichi Nakamura, Kouhei Hosokawa (NEC) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, May 8 PM (14:45 - 15:35) ---------------------------------------- (2) 14:45 - 15:10 Checker Circuit Generation for System Verilog Assertions in Prototyping Verification Mengru Wang, Shinji Kimura (Waseda Univ.) (3) 15:10 - 15:35 Checker Generation of Assertions with Local Variables for Model Checking Sho Takeuchi, Kiyoharu Hamaguchi, Yosuke Kakiuchi, Toshinobu Kashiwabara (Osaka Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, May 8 PM (15:50 - 17:05) ---------------------------------------- (4) 15:50 - 16:15 Improvement Technique of Binding for Multiplexer Reduction Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) (5) 16:15 - 16:40 Radix-2 Butterfly Circuit Architecture Using Selector Logic Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) (6) 16:40 - 17:05 Improvement of swtching activity aware algorithm for prefix graph synthesis Taeko Matsunaga, Shinji Kimura (Waseda Univ), Yusuke Matsunaga (Kyushu Univ) ---------------------------------------- Fri, May 9 AM (10:00 - 11:00) ---------------------------------------- (7) 10:00 - 11:00 [Invited Talk] NoizeProblems in LSI Design:Challenges and Approaches Makoto Nagata (Kobe Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, May 9 AM (11:15 - 12:05) ---------------------------------------- (8) 11:15 - 11:40 Fast Wire Length Estimation in Obstructive Block Placement Shuting Li (Univ. of Kitakyushu), Tan Yan (Univ. of Illinois at Urbana-Champaign), Yasuhiro Takashima, Hiroshi Murata (Univ. of Kitakyushu) (9) 11:40 - 12:05 Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) ----- Break ( 85 min. ) ----- ---------------------------------------- Fri, May 9 PM (13:30 - 14:20) ---------------------------------------- (10) 13:30 - 13:55 Fine-Grained Power Gating Based on the Controlling Value of Logic Gates Lei Chen (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) (11) 13:55 - 14:20 A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, May 9 PM (14:35 - 15:25) ---------------------------------------- (12) 14:35 - 15:00 A Dependable SRAM with high-reliability mode and high-speed mode. Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) (13) 15:00 - 15:25 On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) # CONFERENCE ANNOUNCEMENT: - Please join us for a banquet on May 8th after the conference. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Thu, Jun 26, 2008 - Fri, Jun 27, 2008: Hokkaido Univ. [Mon, Apr 7] # SECRETARY: Hiroyuki OCHI (Kyoto Univ.) E-mail:o    ee k  -u Tel.075-753-4803 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # SECRETARY: Tohru ISHIHARA System LSI Research Center, Kyushu Univ. 3-8-33, Momochihama, Sawara-ku, Fukuoka, 814-0001 TEL: 092-847-5188 FAX: 092-847-5190 Email: i    slrck shu-u# ANNOUNCEMENT: # Please visit us at http://www.ipsj.or.jp/sig/sldm/ Last modified: 2008-05-07 18:33:36 |
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