Mon, Oct 26 AM 09:00 - 10:15 |
(1) |
09:00-09:25 |
Examination of requirements for power side-channel attack resistance evaluation boards of cryptographic integrated circuits
-- PDN transfer impedance contributing to leakage strength -- |
Tomonobu Kan, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) |
(2) |
09:25-09:50 |
Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware |
Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU) |
(3) |
09:50-10:15 |
Fundamental Evaluation Method of EM Information Leakage Caused by Intentional Electromagnetic Interference
-- Impact of Impedance Change in Digital Output Circuits -- |
Shugo Kaji, Daisuke Fujimoto (NAIST), Masahiro Kinugawa (Univ. of Fukuchiyama), Yuichi Hayashi (NAIST) |
|
10:15-10:30 |
Break ( 15 min. ) |
Mon, Oct 26 AM 10:30 - 11:45 |
(4) |
10:30-10:55 |
Laser-based Attacks on Ultrasonic Sensors |
Tatsuya Suehiro, Taku Toyama, Junichi Sakamoto, Tsutomu Matsumoto (Yokohama National Univ.) |
(5) |
10:55-11:20 |
Probing Attack on Share-Serial Threshold Implementation of AES |
Takeshi Sugawara, Yang Li, Kazuo Sakiyama (UEC) |
(6) |
11:20-11:45 |
Feasibility of lattice attacks on ECDSA |
Kotaro Abe, Makoto Ikeda (Tokyo Univ.) |
|
11:45-13:00 |
Lunch Break [ ( 75 min. ) |
Mon, Oct 26 PM 13:00 - 14:15 |
(7) |
13:00-13:25 |
Design of Efficient AES Hardware with Immediately Fault Detection Capability |
Yusuke Yagyu, Rei Ueno, Naofumi Homma (Tohoku Univ.) |
(8) |
13:25-13:50 |
N/A |
Kazunari Takasaki (Waseda Univ.), Ryoichi Kida (LAC), Nozomu Togawa (Waseda Univ.) |
(9) |
13:50-14:15 |
Security Threats and Preventions for Photonics Computing Model |
Junko Takahashi, Koji Chida, Takeshi Sakamoto (NTT) |
|
14:15-14:30 |
Break ( 15 min. ) |
Mon, Oct 26 PM 14:30 - 16:10 |
(10) |
14:30-14:55 |
Domestic Hardware Trojan Research Trends |
Shinichi Kawamura, Yu-ich Hayashi (AIST) |
(11) |
14:55-15:20 |
Physical-Level Detection Approach against Hardware Trojans inside Semiconductor Chips (II) |
Hirofumi Sakane, Shinichi Kawamura, Kentaro Imafuku, Yohei Hori, Makoto Nagata, Yuichi Hayashi, Tsutomu Matsumoto (AIST) |
(12) |
15:20-15:45 |
Hardware Trojan using LUT Structure of AI Inference Devices |
Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ.) |
(13) |
15:45-16:10 |
Low-Latency Countermeasure Circuit Oriented Hardware Trojan and its Evaluation |
Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
|
16:10-16:25 |
Break ( 15 min. ) |
Mon, Oct 26 PM 16:25 - 18:05 |
(14) |
16:25-16:50 |
A Detection Method for Hardware Trojans Inserted into Cryptographic Hardware Netlists |
Akira Ito, Rei Ueno, Naofumi Homma (Tohoku Univ.) |
(15) |
16:50-17:15 |
N/A |
Tatsuki Kurihara, Nozomu Togawa (Waseda Univ.) |
(16) |
17:15-17:40 |
N/A |
Kohei Nozawa (Waseda Univ.), Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto (KDDI Research, Inc.), Nozomu Togawa (Waseda Univ.) |
(17) |
17:40-18:05 |
Investigation of High-Efficiency Simulation Method for Detection of Physical Design Falsification in Secure IC Chip |
Kazuki Yasuda, Kazuki Monta, Daichi Nakagawa, Makoto Nagata (Kobe Univ.) |