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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Kunio Uchiyama (Hitachi) Vice Chair: Masahiko Yoshimoto (Kobe Univ.), Toshihiko Hamasaki (TI)
Secretary: Minoru Fujishima (Hiroshima Univ.), Yoshio Hirose (Fujitsu Labs.)
Assistant: Hiroaki Suzuki (Renesas), Toshimasa Matsuoka (Osaka Univ.), Kenichi Okada (Tokyo Inst. of Tech.)

DATE:
Mon, Dec 14, 2009 10:00 - 17:40
Tue, Dec 15, 2009 10:00 - 17:25

PLACE:

TOPICS:

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Mon, Dec 14 AM (10:00 - 11:40)
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(1) 10:00 - 10:50
[Invited Talk]
Image Sensor
-- An absorbing device with the hardest design --
Satoshi Aoyama, Park Jong-Ho, Takashi Watanabe (Brookman Tech.), Shoji Kawahito (Brookman Tech./Shizuoka Univ.)

(2) 10:50 - 11:40
[Invited Talk]
Experimental Evaluation Technique for Power Supply Noise and Logical Operation Failure
Mitsuya Fukazawa (Renesas Technology Corp.), Makoto Nagata (Kobe Univ.)

----- Lunch Break -----

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Mon, Dec 14 PM (13:30 - 17:40)
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(3) 13:30 - 16:40
[Poster Presentation]
Reducing pattern area technology of 3D transistor for system LSI
Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

(4) 13:30 - 16:40
[Poster Presentation]
Design Technology of stacked NAND type MRAM
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

(5) 13:30 - 16:40
[Poster Presentation]
Design Technology of stacked NAND type 1-transistor FeRAM
Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech)

(6) 13:30 - 16:40
[Poster Presentation]
Simulation of Substrate Noise Impact on CMOS Analog Circuit
Satoshi Takaya, Yoji Bando, Makoto Nagata (Kobe Univ.)

(7) 13:30 - 16:40
[Poster Presentation]
Modeling of power supply noise on CMOS digital circuits
Daisuke Fujimoto, Tetsuro Matsuno, Makoto Nagata (Kobe Univ.)

(8) 13:30 - 16:40
[Poster Presentation]
Measurement and Simulation of Substrate Coupling of CMOS-RF Circuit
Naoya Azuma, Makoto Nagata (Kobe Univ.)

(9) 13:30 - 16:40
[Poster Presentation]
Design Optimization of High-Speed, High-Gain OTA with gm/Id Lookup Table Method
Takayuki Konishi, Shoichi Masui (Tohoku Univ.)

(10) 13:30 - 16:40
[Poster Presentation]
Ultra-Low Voltage 2-stage Amplifier Circuit with Wide Input/Output Range
Ryosuke Takahashi, Tomochika Harada, Sumio Okuyama, Koichi Matsushita (Yamagata Univ.)

(11) 13:30 - 16:40
[Poster Presentation]
Process Variation Compensation Technique for 0.5-V Body-Input Comparator
Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.)

(12) 13:30 - 16:40
[Poster Presentation]
A Design of Parallel Analog-to-Digital Converter Utilizing Process Variations
Hyunju Ham, Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.)

(13) 13:30 - 16:40
[Poster Presentation]
A nanowatt DA converter for subthreshold CMOS LSIs
Kazuki Yamamoto, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.)

(14) 13:30 - 16:40
[Poster Presentation]
Intermittent Pulse Generator for Ultra-Low Power LSIs
Hiromichi Matsushita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.)

(15) 13:30 - 16:40
[Poster Presentation]
A CMOS Image Sensor for Car-to-Car/Road-to-Car Optical Comunication Systems and evaluation Experiment of Communication Distance with LED Source of Light
Moeta Hamai, Shinya Itoh, Md. Shakowat Zaman Sarker, Keita Yasutomi (Shizuoka Univ.), Isamu Takai, Michinori Andoh (TOYOTA Central R&D Labs..Inc.), Shoji Kawahito (Shizuoka Univ.)

(16) 13:30 - 16:40
[Poster Presentation]
An evaluation of delay error rate of an adder in terms of clock period
Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi (Osaka Univ.)

(17) 13:30 - 16:40
[Poster Presentation]
An Improved Face-Detection Method for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1
Hirokazu Hiramoto, Takeshi Kumaki, Yuta Imai, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.)

(18) 13:30 - 16:40
[Poster Presentation]
Associative-Memory-Based LSI with Adaptive-Learning Capability
Akio Kawabata, Wataru Imafuku, Tania Ansari, Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.)

(19) 13:30 - 16:40
[Poster Presentation]
Development of a Stream Cipher Engine Chip
Takumi Ishihara, Harunobu Uchiumi, Yusuke Osumi, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.)

----- Break ( 20 min. ) -----

(20) 17:00 - 17:40

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Tue, Dec 15 AM (10:00 - 11:40)
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(21) 10:00 - 10:50
[Invited Talk]
A New VLSI System Architecture Mimicking the Processing in the Mind
Tadashi Shibata (Univ. of Tokyo.)

(22) 10:50 - 11:40
[Invited Talk]
History and Technology Trends of Si RF Analog LSI Developments
-- Emergence of New-Type Circuit Designers --
Tsuneo Tsukahara (Univ. of Aizu)

----- Lunch Break -----

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Tue, Dec 15 PM (13:30 - 15:35)
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(23) 13:30 - 13:55
A remote optically reconfigurable gate array with 4 configuration contexts
Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.)

(24) 13:55 - 14:20
Wide Swing, Low Gain Error Voltage Buffer with Adaptive Biasing for Improving Slew-rate
Jagatjyoti Ghimire, Cong-Kha Pham (The Univ. of Electro-comm.)

(25) 14:20 - 14:45
Design of High Resolution Continuous-Time Bandpass Delta-Sigma AD Modulator
Haijun Lin, Atushi Motozawa (Gunma Univ.), Pascal Lo Re, Kunihiko Iizuka (Sharp Corp.), Haruo Kobayashi (Gunma Univ.), Hao San (Tokyo City Univ.), Nobukazu Takai (Gunma Univ.)

(26) 14:45 - 15:10
Sturdy-MASH-type ΔΣAD Modulator with Wide Dynamic Range
Takafumi Yamada, Hajime Konagaya (Gunma Univ), Hao San (Tokyo City Univ), Haruo Kobayashi (Gunma Univ)

(27) 15:10 - 15:35
Non-binary SAR ADC with Digital Compensation of Comparator Offset Effect
Tomohiko Ogawa (Gunma Univ), Tatsuji Mtsuura (Renesas), Haruo Kobayashi, Nobukazu Takai (Gunma Univ), Masao Hotta, Hao San (Tokyo City Univ)

----- Break ( 10 min. ) -----

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Tue, Dec 15 PM (15:45 - 17:25)
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(28) 15:45 - 16:10
A Simple High Efficiency DC-DC Converter Adaptive to Input Voltage and Load Current
Pin Zhang, Cong-Kha Pham (The Univ. of Electro-Comm.)

(29) 16:10 - 16:35
Inductor Design of 20-V Boost Converter for Low Power 3D Solid State Drive
Tadashi Yasufuku, Koichi Ishida (Univ. of Tokyo.), Shinji Miyamoto, Hiroto Nakai (Toshiba), Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi (Univ. of Tokyo.)

(30) 16:35 - 17:00
Bandwidth Enhancement for TIA with Mutually Coupled Inductors
Yoshihiro Okumura (Kyoto Univ.), Makoto Nakamura (NTT), Keiji Kishine (University of Shiga Prefecture), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.)

(31) 17:00 - 17:25
A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM --
Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
Invited Talk will have 40 minutes for presentation and 10 minutes for discussion.

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, Jan 28, 2010 - Fri, Jan 29, 2010: T.B.D. [Tue, Nov 17]
Mon, Mar 1, 2010: Kyushu Univ. [Mon, Feb 1], Topics: Technical Meeting on Silicon Analog RF Technologies

# SECRETARY:
Toshimasa Matsuoka (Osaka University)
TEL 06-6879-7792, FAX 06-6879-7792
E-mail: