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Technical Committee on VLSI Design Technologies (VLD)
Chair: Nagisa Ishiura (Kwansei Gakuin Univ.) Vice Chair: Kazutoshi Wakabayashi (NEC)
Secretary: Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas)

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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Akira Matsuzawa (Tokyo Inst. of Tech.) Vice Chair: Kunio Uchiyama (Hitachi)
Secretary: Yoshiharu Aimoto (NECEL), Makoto Nagata (Kobe Univ.)
Assistant: Minoru Fujishima (Univ. of Tokyo), Yoshio Hirose (Fujitsu Labs.)

DATE:
Wed, Mar 5, 2008 13:00 - 17:10
Thu, Mar 6, 2008 09:15 - 17:00
Fri, Mar 7, 2008 09:15 - 17:25

PLACE:

TOPICS:
System-on-silicon design techniques and related VLSs

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Wed, Mar 5 PM (13:00 - 15:05)
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(1) 13:00 - 13:25
Automatic synthesis and verification of practical protocol transducer based on product graph exploration
Yuji Ishikawa (Univ. of Tokyo), Satoshi Komatsu, Masahiro Fujita (VDEC, Univ. of Tokyo)

(2) 13:25 - 13:50
Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems
Makoto Sugihara (TUT)

(3) 13:50 - 14:15
An accurate Algorithm for RTL Power Macro-modeling
Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui (Ritsumeikan Univ.)

(4) 14:15 - 14:40
Minimizing Minimum Delay Compensations in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)

(5) 14:40 - 15:05
An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory
Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

----- Break ( 15 min. ) -----

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Wed, Mar 5 PM (15:20 - 17:10)
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(6) 15:20 - 15:45
Analog Floorplan with Soft-Module Configuration
Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)

(7) 15:45 - 16:10
MOS Analog Module Generation
Akio Fujii, Takehiko Matsuo, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu)

(8) 16:10 - 17:10
[Fellow Memorial Lecture]
Research on VLSI Design and its Future
Hiroaki Kunieda (Tokyo Inst. Tech.)

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Thu, Mar 6 AM (09:15 - 10:55)
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(9) 09:15 - 09:40
A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration
Tetsuro Ikeda, Atsushi Iwata (Hiroshima Univ.)

(10) 09:40 - 10:05
A-90dBm Sensitivity 0.13μm CMOS Bluetooth Transceiver Operating in Wide Temperature Range
Kenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shinichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa (Toshiba)

(11) 10:05 - 10:30
Design and Analysis of on-chip leakage monitor using MTCMOS
Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami (S.I.T.)

(12) 10:30 - 10:55
Design and Evaluation of the component circuits for the PLL
Yuko Kitaji, Masayoshi Tachibana (Kochi Univ. of Tech.)

----- Break ( 15 min. ) -----

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Thu, Mar 6 AM (11:10 - 12:25)
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(13) 11:10 - 11:35
Implementation of LCD Driver by nMOS Dynamic Logic
Takuya Hachida, Hideki Matsunaka, Isao Shirakawa (Hyogo Pref. Univ.), Shuji Tsukiyama (Chuo Univ.), Masanori Hashimoto (Osaka Univ.)

(14) 11:35 - 12:00
A Study for Implementation of High Speed Circuit Simulator by using FPGA
Taiki Hashizume, Seiji Minoura, Tadashi Mizutani, Hironobu Ishijima, Shinichi Nishizawa (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Masahiro Fukui (Ritsumeikan Univ.)

(15) 12:00 - 12:25
Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders
Masayoshi Tachibana (kochi University of Technology)

----- Lunch Break ( 60 min. ) -----

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Thu, Mar 6 PM (13:25 - 15:30)
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(16) 13:25 - 14:15
[Invited Talk]
Self descriptive verfication in Continuation based C and it's application to Cell architecture
Shinji Kono (University of the Ryukyus)

(17) 14:15 - 14:40
Conversion to CbC which used the Cell architecture from C
Akira Kamizato, Shinji Kono (Univ of ryukyu)

(18) 14:40 - 15:05
A Case Study on MPEG4 Decoder Design with SystemBuilder
Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)

(19) 15:05 - 15:30
Performance Estimation considering False-paths for System-level Design
Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo)

----- Break ( 15 min. ) -----

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Thu, Mar 6 PM (15:45 - 17:00)
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(20) 15:45 - 16:10
Superposition Effect Validation of Inductive Coupling Noise Based on Measurement of Interconnect Delay Variation
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.)

(21) 16:10 - 16:35
Global Routing Method of Plating Lead for 2-Layer BGA Packages
Naoki Sato, Yoichi Tomioka, Atsushi Takahashi (Tokyo Tech)

(22) 16:35 - 17:00
Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI
Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

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Fri, Mar 7 AM (09:15 - 10:30)
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(23) 09:15 - 09:40
A delay balancing technique for wave-pipelining
Keiichiro Sano, Jubee Tada (Yamagata Univ), Ryusuke Egawa (Touhoku Univ), Gensuke Goto (Yamagata Univ)

(24) 09:40 - 10:05
Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit
Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.)

(25) 10:05 - 10:30
A Self-timed Processor with Dynamic Voltage Scaling
Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo)

----- Break ( 15 min. ) -----

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Fri, Mar 7 AM (10:45 - 12:00)
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(26) 10:45 - 11:10
A High-Throughput Architectures for LDPC Coded OFDM Baseband Processor
Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.)

(27) 11:10 - 11:35
Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule
Yuta Abe, Naoki Tajima, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)

(28) 11:35 - 12:00
Low Power Design of Accelerated Message-Passing LDPC Decoder for Long Codes
Naoki Tajima, Yuta Abe, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)

----- Lunch Break ( 60 min. ) -----

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Fri, Mar 7 PM (13:00 - 15:05)
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(29) 13:00 - 13:25
The Improvement of the Ubiqitus Processor HCgorilla
Hiroki Takeda, Kazunori Noda, Atuko Yokoyama, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ)

(30) 13:25 - 13:50
An adaptive error concealment order H.264/AVC
Jun Wang, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)

(31) 13:50 - 14:15
A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs
Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)

(32) 14:15 - 14:40
Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method
Motonori Ohta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ)

(33) 14:40 - 15:05
Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX)
Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.)

----- Break ( 15 min. ) -----

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Fri, Mar 7 PM (15:20 - 17:25)
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(34) 15:20 - 15:45
An Object Oriented System LSI Design Methodology and Its Evaluation
Takafumi Kohara, Hiroyuki Terai, Seigo Masuoka (Kinki University), Akihisa Yamada (SHARP Corp.), Takashi Kambe (Kinki University)

(35) 15:45 - 16:10
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor
Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University)

(36) 16:10 - 16:35
New technology of independent-gate controlled Double-Gate transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

(37) 16:35 - 17:00
New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

(38) 17:00 - 17:25
Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Thu, May 8, 2008 - Fri, May 9, 2008: Kobe Univ. [Mon, Mar 17], Topics: System Design, etc.
Thu, Jun 26, 2008 - Fri, Jun 27, 2008: Hokkaido Univ. [Mon, Apr 7]

# SECRETARY:
Hiroyuki OCHI (Kyoto Univ.)
E-mail:o

-u

Tel.075-753-4803

# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, Apr 17, 2008 - Fri, Apr 18, 2008: [Mon, Feb 18]
Tue, May 13, 2008 - Wed, May 14, 2008: [Mon, Mar 24]

# SECRETARY:
Yoshio Hirose (Fujitsu Laboratories Ltd.)
TEL +81-44-754-2783, +81-44-754-2744
E-mail:y