Thu, Oct 1 AM 09:10 - 10:50 |
(1) |
09:10-09:35 |
Feasibility Study on EMI Measurement "furoshiki" using 2V Organic CMOS and Silicon CMOS |
Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani (Univ. of Tokyo), Ute Zschieschang, Hagen Klauk (Max Planck Institute), Makoto Takamiya, Takao Someya, Takayasu Sakurai (Univ. of Tokyo) |
(2) |
09:35-10:00 |
A 6-bit Arbitrary Digital Noise Emulator in 65nm CMOS Technology |
Daisuke Fujimoto, Tetsuro Matsuno (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi (Toshiba Corp.), Makoto Nagata (Kobe Univ./A-R-Tec) |
(3) |
10:00-10:25 |
Evaluation and Analysis of Substrate Noise in Microprocessor |
Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) |
(4) |
10:25-10:50 |
Chip-to-Chip Half Duplex Data Communication at 135 Mbps Over Power-Supply Rails |
Takushi Hashida, Makoto Nagata (Kobe Univ.) |
|
10:50-11:00 |
Break ( 10 min. ) |
Thu, Oct 1 AM 11:00 - 12:40 |
(5) |
11:00-11:25 |
A 0.2mm2, 27Mbps 3mW ADC/FFT-less FDM BAN receiver with energy exploitation capability |
Haruya Ishizaki, Masayuki Mizuno (NEC) |
(6) |
11:25-11:50 |
Implementation of a Time-of-Flight Image Sensor using High Speed Charge Transfer Pinned-Photodiodes |
Hiroaki Takeshita, Tomonari Sawada, Tetsuya Iida, Keita Yasutomi, Shoji Kawahito (Shizuoka Univ.) |
(7) |
11:50-12:15 |
Time Domain Fluorescence Lifetime Image Sensor Using Two-Stage Charge Transfer Pixels with Pinned Diode |
Zhuo Li (Shizuoka Univ.), Hyung-June Yoon (Delft Univ. of Tech.), Shinya Ito, Shoji Kawahito (Shizuoka Univ.) |
(8) |
12:15-12:40 |
CMOS image sensor for optical measurement of cranial nerve activity |
Yasuhiro Oguro, Sanshiro Shishido (NAIST), Toshihiko Noda, Kiyotaka Sasagawa, Takashi Tokuda, Jun Ohta (NAIST/JST) |
|
12:40-13:30 |
Lunch Break ( 50 min. ) |
Thu, Oct 1 PM 13:30 - 15:10 |
(9) |
13:30-13:55 |
Development of a multifunctional CMOS image sensor for in vivo sensing of neural activities in a mouse deep brain |
Ayato Tagawa, Hiroki Mitani, Masahiro Mitani (NAIST), Toshihiko Noda, Kiyotaka Sasagawa, Takashi Tokuda, Jun Ohta (NAIST/JST) |
(10) |
13:55-14:20 |
CMOS Analog Integrated Circuits for On-Chip Biosensing |
Kazuo Nakazato (Nagoya Univ.) |
(11) |
14:20-15:10 |
[Invited Talk]
Smart Micro Chips with Sensor Array and IC for Bio/Medical Applications |
Makoto Ishida, Takeshi Kawano, Kazuaki Sawada (Toyohashi Univ. of Tech./JST) |
|
15:10-15:20 |
Break ( 10 min. ) |
Thu, Oct 1 PM 15:20 - 18:35 |
(12) |
15:20-16:10 |
[Invited Talk]
Integrated MEMS and Biomedical MEMS |
Masayoshi Esashi (Tohoku Univ.) |
(13) |
16:10-17:00 |
[Invited Talk]
Bio/chemical sensors for novel physical monitoring |
Kohji Mitsubayashi (Tokyo Medical & Dental Univ.) |
|
17:00-17:05 |
Break ( 5 min. ) |
(14) |
17:05-18:35 |
|
Fri, Oct 2 AM 09:10 - 10:50 |
(15) |
09:10-09:35 |
Study of Active Substrate Noise Cancelling Technique using PowerLine di/dt Detector |
Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) |
(16) |
09:35-10:00 |
Meta-Stable Characteristic of Single-Slope ADC with Time to Digital Convertor for CMOS-imager Sensor |
Shin Muon, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.) |
(17) |
10:00-10:25 |
Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits |
Dong Ta Ngoc Huy, Masaya Miyahara, Akira Matsuzawa (Tokyo Inst. of Tech.) |
(18) |
10:25-10:50 |
A 0.5 V Feedforward Delta-Sigma Modulator with CMOS Inverter-Based Integrator |
Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) |
|
10:50-11:00 |
Break ( 10 min. ) |
Fri, Oct 2 AM 11:00 - 13:05 |
(19) |
11:00-11:50 |
[Invited Talk]
AD Conversion Principles and CMOS Circuit Techniques |
Atsushi Iwata (A-R-Tec) |
(20) |
11:50-12:15 |
An 8-bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques |
Daehwa Paik, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa (Tokyo Inst. of Tech.) |
(21) |
12:15-12:40 |
Digital Correction Algorithm of Timing Skew Effects in Time-Interleave ADC Systems |
Koji Asami (Advantest), Tsuyoshi Kurosawa, Takenori Tateiwa, Hiroyuki Miyajima, Haruo Kobayashi (Gunma Univ.) |
(22) |
12:40-13:05 |
A Self-Background Calibrated 6b 2.7GS/s ADC with Cascade-Calibrated Folding-Interpolating Architecture |
Yuji Nakajima (NEC Electronics), Akemi Sakaguchi, Toshio Ohkido (NEC Micro Systems), Tetsuya Matsumoto, Michio Yotsuyanagi (NEC Electronics) |
|
13:05-13:55 |
Lunch Break ( 50 min. ) |
Fri, Oct 2 PM 13:55 - 16:00 |
(23) |
13:55-14:45 |
[Invited Talk]
Technical Trend of RF circuits |
Satoshi Tanaka (Renesas Tech Corp.) |
(24) |
14:45-15:10 |
A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications |
Toshiya Mitomo, Naoko Ono, Hiroaki Hoshino, Yoshiaki Yoshihara, Osamu Watanabe, Ichiro Seto (Toshiba) |
(25) |
15:10-15:35 |
A High Image-Rejection 24-GHzBand Low Noise Amplifier |
Toru Masuda, Nobuhiro Shiramizu, Takahiro Nakamura, Katsuyoshi Washio (Hitachi) |
(26) |
15:35-16:00 |
Low-Power Zero-IF Full-segment ISDB-T CMOS Tuner with 10th-Order Channel Filters |
Takatusugu Kamata (Osaka Univ./RfStream Corp.), Kazunori Okui, Masahiko Fukasawa, Kazuyoshi Tanaka, Go Chyuki (RfStream Corp.), Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) |
|
16:00-16:10 |
Break ( 10 min. ) |
Fri, Oct 2 PM 16:10 - 18:15 |
(27) |
16:10-16:35 |
A 58-uW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol |
Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) |
(28) |
16:35-17:00 |
A High Linear and Wide Frequency Range RF Sampling Circuit for Discrete Time Signal Processing |
Mamoru Sato, Hiroyuki Abe, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) |
(29) |
17:00-17:25 |
100-1000 MHz Cutoff Frequency, 0-12 dB Boost Programmable Gm-C Filter with Digital Calibration for HDD Read Channel |
Takahide Terada (Hitachi, Ltd.), Koji Nasu (Renesas Tech Corp.), Taizo Yamawaki, Masaru Kokubo (Hitachi, Ltd.) |
(30) |
17:25-17:50 |
A fully-integrated clock reference generator with frequency-locked loop |
Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) |
(31) |
17:50-18:15 |
Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power |
Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) |