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| Chair |
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MIchitaka Kameyama |
| Vice Chair |
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Masao Nakaya |
| Secretary |
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Kunio Uchiyama, Shinji Miyano |
| Assistant |
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Masanori Hariyama, Koji Kai |
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| Conference Date |
Thu, Apr 14, 2005 09:00 - 21:00
Fri, Apr 15, 2005 10:30 - 15:00 |
| Topics |
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| Conference Place |
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Thu, Apr 14 AM
09:00 - 10:30 |
| (1) |
09:00-09:30 |
A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications |
Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL) |
| (2) |
09:30-10:00 |
Low-Power Embedded SRAM Modules with Expanded Margins for Writing |
Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
| (3) |
10:00-10:30 |
A 256Mb Synchronous Burst DDR SRAM using Single-crystal Silicon Thin Film Transisitor (SSTFT) SRAM cell |
Youngho Suh, Hyouyoun Nam, Youngdae Lee, Hungiun An, Sangbeom Kang, Byunggil Choi, Hoon Lim, Choongkeun Kwak, Hyunguen Byun (Samsung) |
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10:30-10:40 |
Break ( 10 min. ) |
Thu, Apr 14 AM
10:40 - 12:10 |
| (4) |
10:40-11:40 |
[Invited Talk]
DRAM in the Nanoscale Era
-- Non-1T1C approaches -- |
Tomoyuki Ishii (Hitachi) |
| (5) |
11:40-12:10 |
A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI |
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
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12:10-13:00 |
Lunch Break ( 50 min. ) |
Thu, Apr 14 PM
13:00 - 15:00 |
| (6) |
13:00-14:00 |
[Invited Talk]
* |
Hiroyuki Yamauchi (Matsushita) |
| (7) |
14:00-14:30 |
A 196-mm2, 2-Gb DDR2 SDRAM using an 80-nm Triple Metal Technology |
Jeong Hoon kook, Kyehyun Kyung, Chiwook Kim, Jaeyoung Lee (Samsung) |
| (8) |
14:30-15:00 |
[Invited Talk]
Statistical Integration In Multigigabit DRAM Design |
Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
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15:00-15:15 |
Break ( 15 min. ) |
Thu, Apr 14 PM
15:15 - 16:45 |
| (9) |
15:15-15:45 |
Improved write methods for 64Mb Phase-change Random Access Memory (PRAM) |
Hyung-rok Oh, Beak-hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-gil Choi, Hye-jin Kim, Ki-sung Kim, Du-eung Kim, Choong-keun Kwak, Hyun-geun Byun, Gi-tae Jeong, Hong-sik Jeong, Kinam Kim (Samsung) |
| (10) |
15:45-16:15 |
A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology |
Takumi Abe, Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka (Toshiba), Teruhiko Kamei, Hiroaki Nasu (SanDisk) |
| (11) |
16:15-16:45 |
4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput |
Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume (Hitachi), Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa (RENESAS) |
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16:45-19:00 |
Break reception ( 135 min. ) |
Thu, Apr 14 PM Evening Panel
19:00 - 21:00 |
| (12) |
19:00-21:00 |
* |
Katsuyuki Sato (Elpida), Hiroyuki Yamauchi (Matsushita), Kenji Numata (Toshiba), Takashi Akazawa (Renesas), Yasunao Katayama (IBM Japan) |
Fri, Apr 15 AM
10:30 - 12:00 |
| (13) |
10:30-11:00 |
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture |
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) |
| (14) |
11:00-11:30 |
High Density and Low Power Nonvolatile FeRAM Memory Cell Architecture |
Takashi Miki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Yasushi Gohou, Eiji Fujii (Matsushita Electric Industrial Co., Ltd.) |
| (15) |
11:30-12:00 |
Burst-Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM |
Ryo Fukuda, Kenji Kobayashi (Toshiba Corp.), Masashi Akamatsu, Minoru Kaihatsu, Atsushi Tamura, Kazuo Taniguchi (Sony Corp.), Yohji Watanabe (Toshiba Corp.) |
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12:00-13:00 |
Lunch Break ( 60 min. ) |
Fri, Apr 15 PM
13:00 - 15:00 |
| (16) |
13:00-13:30 |
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell
-- High Speed and Low-Power Operation by Using Dual-Wordline Scheme -- |
Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL) |
| (17) |
13:30-14:00 |
Application of Bank-Based Multiport Memory to the Microprocessor Caches |
Koh Johguchi, Zhaomin Zhu (Hiroshima Univ.), Tai Hirakawa (Hiroshima City Univ.), Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.), Tetsuo Hironaka, Kazuya Tanigawa (Hiroshima City Univ.) |
| (18) |
14:00-14:30 |
Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes |
Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi) |
| (19) |
14:30-15:00 |
New Development of Neutron-induced Soft-Error Simulation Technology |
Taiki Uemura, Yoshiharu Tosaka, Yoshio Ashizawa, Hideki Oka, Shigeo Satoh (Fujitsu lab.) |
| Contact Address and Latest Schedule Information |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
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| Contact Address |
Shinji Miyano (Toshiba)
TEL +81-44-548-2696, FAX +81-44-548-8324
E- :  n       ba |
Last modified: 2005-03-30 20:08:03
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