Tue, Feb 28 AM 11:00 - 11:50 |
(1) |
11:00-11:25 |
|
Takumi Sugioka, Yoshikazu Nagamura (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
(2) |
11:25-11:50 |
A Test Generation Method to Distinguish Multiple Fault Pairs for Improvement of Fault Diagnosis Resolution |
Yuya Chida, Toshinori Hosokawa (NIhon Univ.), Koji Yamazaki (Meiji Univ.) |
|
11:50-13:00 |
Break ( 70 min. ) |
Tue, Feb 28 PM 13:00 - 14:15 |
(3) |
13:00-13:25 |
|
Taito Asaji, Tatsuhiro Tsuchiya (Osaka Univ.) |
(4) |
13:25-13:50 |
A Clear and Understandable Notation for Expressing T-Way Test Sequence Generation Constraints |
Lele Jiang, Tatsuhiro Tsuchiya (Osaka Univ.) |
(5) |
13:50-14:15 |
Analysis of the Relationship between the Error Recovery and Reliability on Approximate Multipliers |
Kozuma, Tamaki, Wang,Qilin, Ichihara, Hideyuki, Inoue, Tomoo (Hiroshima City Univ.) |
|
14:15-14:25 |
Break ( 10 min. ) |
Tue, Feb 28 PM 14:25 - 15:40 |
(6) |
14:25-14:50 |
Test Point Selection Method Using Graph Neural Networks and Deep Reinforcement Learning |
Shaoqi Wei, Kohei Shiotani, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
(7) |
14:50-15:15 |
A Don't-Care Filling Method of Control Signals on Controllers for Two-Pattern Concurrent Testing |
Xu Haofeng, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (KSU), Arai Masayuki (Nihon Univ.) |
(8) |
15:15-15:40 |
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST |
Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU) |
|
15:40-15:50 |
Break ( 10 min. ) |
Tue, Feb 28 PM 15:50 - 17:05 |
(9) |
15:50-16:15 |
Stochastic flash ADC with variable input voltage range |
Taira Sakaguchi, Satoshi Komatsu (Tokyo Denki Univ.) |
(10) |
16:15-16:40 |
A Novel High Performance Scan-Test-Aware Hardened Latch with Improved Soft Error Tolerability |
Ruijun Ma (AUST), Stefan Holst, Xiaoqing Wen (KIT), Hui Xu (AUST), Aibin Yan (AU) |
(11) |
16:40-17:05 |
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuit |
Taiki Utsunomiya, Kohei Miyase, Ryu Hoshino (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) |