Thu, Dec 11 AM
10:00 - 12:00 |
| (1) |
10:00-10:10 |
|
| (2) |
10:10-11:00 |
[Special Invited Talk]
Advancement and Prospect of Video Codec Processors for Multi Media Era |
Tadayoshi Enomoto (Chuo Univ.) |
| |
11:00-11:10 |
Break ( 10 min. ) |
| (3) |
11:10-12:00 |
[Invited Talk]
Recollections of Pleasure and Troubles in Analog Circuit Design |
Yasuhiro Sugimoto (Chuo Univ.) |
| |
12:00-13:30 |
Luch Break ( 90 min. ) |
Thu, Dec 11 PM
13:30 - 17:10 |
| (4) |
13:30-16:15 |
[Poster Presentation]
Buried Photodiode Structure for High-Speed Charge Transfer |
Hiroaki Takeshita, Tomonari Sawada, Kana Ito, Tomohiro Iwahori, Shoji Kawahito (Shizuoka Univ.) |
| (5) |
13:30-16:15 |
[Poster Presentation]
Noise reduction effect of sloped reset for Readout circuitry of image sensors |
Tetsuya Iida, Shinya Itoh, Shoji Kawahito (Shizuoka Univ.) |
| (6) |
13:30-16:15 |
[Poster Presentation]
Device Modeling of On-Chip Capacitors for Millimeter-Wave Applications |
Youhei Natsukari, Minoru Fujishima (Tokyo Univ.) |
| (7) |
13:30-16:15 |
[Poster Presentation]
Frequency Synthesizer Utilizing Injection Locking |
Fan Wang, Minoru Fujishima (Tokyo Univ.) |
| (8) |
13:30-16:15 |
[Poster Presentation]
On-Chip S-Shaped Rat-Race Balun for Millimeter-Wave Band Using W-CSP Process |
Yasuo Manzawa, Chiaki Inui, Minoru Fujishima (Tokyo Univ) |
| (9) |
13:30-16:15 |
[Poster Presentation]
60GHz CMOS Pulse Generator |
Wasanthamala Badalawa, Minoru Fujishima (Tokyo Univ) |
| (10) |
13:30-16:15 |
[Poster Presentation]
Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring |
Yuuki Araga, Takushi Hashida, Makoto Nagata (Kobe Univ.) |
| (11) |
13:30-16:15 |
[Poster Presentation]
EMC analysis of LSI
-- Evaluation and simulation of on-chip and on-board power supply noise -- |
Kumpei Yoshikawa, Makoto Nagata (Kobe Univ.) |
| (12) |
13:30-16:15 |
[Poster Presentation]
Simulation Techniques for Power Supply Noise and Operation Failures in Digital LSI |
Takuya Sawada, Makoto Nagata (Kobe Univ.) |
| (13) |
13:30-16:15 |
[Poster Presentation]
3.3mW 11-times CMOS Frequency Multiplier |
Seong Woong Lim, Minoru Fujishima (Tokyo Univ.) |
| (14) |
13:30-16:15 |
[Poster Presentation]
Design Automated for Millimeter-Wave Mixers |
Sho Ohashi, Minoru Fujishima (The Univ. of Tokyo) |
| (15) |
13:30-16:15 |
[Poster Presentation]
A Multi-Stage 60GHz CMOS LNA Using Dual Noise-Matching Technique |
Ning Li, Kenichi Okada (Tokyo Tech.), Toshihide Suzuki, Tatsuya Hirose (Fujitsu Lab), Akira Matsuzawa (Tokyo Tech.) |
| (16) |
13:30-16:15 |
[Poster Presentation]
Design of Low-Power Medical Devices |
Kenichi Matsunaga, Vo Minh Tuan, Satoshi Furuya, Takashi Kurashina, Akira Matsuzawa (Titech) |
| (17) |
13:30-16:15 |
[Poster Presentation]
A 65fJ/b Inductive-Coupling Inter-Chip Transciever for Low-Power 3D System Integration |
Kiichi Niitsu, Noriyuki Miura, Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) |
| (18) |
13:30-16:15 |
[Poster Presentation]
Contact Resistance Modeling of MEMS Scanner for CMOS-MEMS Simultaneous Simulation |
Yuheon Yi, Hiroyuki Fujita, Hiroshi Toshiyoshi (U. of Tokyo) |
| (19) |
13:30-16:15 |
[Poster Presentation]
Fast optical reconfigurations of a nine-context DORGA |
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) |
| (20) |
13:30-16:15 |
[Poster Presentation]
Performance estimation for a gate array part of a dynamic optically reconfigurable gate array |
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) |
| |
16:15-16:30 |
Break ( 15 min. ) |
| (21) |
16:30-17:10 |
|
Fri, Dec 12 AM
10:00 - 11:50 |
| (22) |
10:00-10:50 |
[Invited Talk]
Prospect of Developping AIPS Robots for Home Total Support ing Systems
-- The key is the combined technology of Software, Mechanical and Electronics -- |
Yoshiaki Hagihara (AIPSコンソーシアム) |
| |
10:50-11:00 |
Break ( 10 min. ) |
| (23) |
11:00-11:50 |
[Invited Talk]
For those who wish to be a integrated circuit designer |
Kenji Taniguchi (Osaka Univ.) |
| |
11:50-13:20 |
Luch Break ( 90 min. ) |
Fri, Dec 12 PM
13:20 - 15:00 |
| (24) |
13:20-13:45 |
Fast Voltage Control Scheme with Adaptive Voltage Control Steps and Temporary Reference Voltage Overshoots for Dynamic Voltage and Frequency Scaling |
Yoshifumi Ikenaga, Masahiro Nomura (NEC Electronics), Yoetsu Nakazawa (NEC Corporation), Yoshihiro Hayashi (NEC Electronics) |
| (25) |
13:45-14:10 |
Improvement of Logic Element used in Via programmable logic device VPEX |
Tomohiro Nishimoto, Masahide Kawarasaki, Eiji Hasegawa, Tomohiro Terakawa, Takeshi Fujino (Ritsumei Univ) |
| (26) |
14:10-14:35 |
The Development of CAD Design Tools for Via Programmable Logic Device VPEX |
Yuuichi Kokushou, Masahide Kawarasaki, Kouta Ishibashi, Tomohiro Nishimoto, Kazuma Kitamura (Ritsumeikan Univ), Masaya Yoshikawa (Meijyou Univ), Takeshi Fujino (Ritsumeikan Univ) |
| (27) |
14:35-15:00 |
Asynchronous ±1 Gray-Code Adder |
Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.) |
| |
15:00-15:20 |
Break ( 20 min. ) |
Fri, Dec 12 PM
15:20 - 17:00 |
| (28) |
15:20-15:45 |
Two-stage Charge Transfer Pixel Fabricated in Standard CMOS Image Sensor Technology |
Keita Yasutomi, Toshihiro Tamura, Shinya Itoh, Shoji Kawahito (Shizuoka Univ.) |
| (29) |
15:45-16:10 |
Low-power Adiabatic Logic Circuit: Simulation and Energy Dissipation Comparison |
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) |
| (30) |
16:10-16:35 |
An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control |
Kosuke Yamaguchi, Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kove Univ) |
| (31) |
16:35-17:00 |
Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology |
Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) |
| |
17:00-17:05 |
Closing Address ( 5 min. ) |
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