ken-system: Advance Program - 2022-01-RECONF-VLD-CPSY-IPSJ-ARC-IPSJ-SLDM

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Technical Committee on VLSI Design Technologies (VLD)

Chair		Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Vice Chair		Minako Ikeda (NTT)
Secretary		Daisuke Kanemoto (Osaka Univ.), Makoto Miyamura (NEC)

Technical Committee on Computer Systems (CPSY)

[schedule] [select]

Chair		Michihiro Koibuchi (NII)
Vice Chair		Kota Nakajima (Fujitsu Lab.), Tomoaki Tsumura (Nagoya Inst. of Tech.)
Secretary		Yasushi Inoguchi (JAIST), Shugo Ogawa (Hitachi)
Assistant		Ryohei Kobayashi (Tsukuba Univ.), Takaaki Miyajima (Meiji Univ.)

Technical Committee on Reconfigurable Systems (RECONF)

[schedule] [select]

Chair		Kentaro Sano (RIKEN)
Vice Chair		Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Secretary		Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)
Assistant		Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.)

Special Interest Group on System Architecture (IPSJ-ARC)

[schedule] [select]

Chair		Hiroshi Inoue (Kyushu Univ.)
Secretary		Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Labs.), Yohei Hasegawa (Toshiba Memory)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)

[schedule] [select]

Chair		Yuichi Nakamura (NEC)
Secretary		Kenshu Seto (Tokyo City Univ.), Kazushi Kawamura (Tokyo Inst. of Tech.), Masayuki Hiromoto (Fujitsu), Hiroki Hosoda (Sony LSI Design)

Conference Date	Mon, Jan 24, 2022 09:30 - 17:35 Tue, Jan 25, 2022 09:30 - 17:30
Topics	FPGA Applications, etc.
Conference Place	Online
Registration Fee	This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF, VLD, CPSY.

Mon, Jan 24 AM 09:30 - 11:10
(1) VLD	09:30-09:55	Study on a Correlation Controlling Method to Realize Correlation-used Calculations Sequentially in Stochastic Computing	Shu Zhang, Shigeru Yamashita (Ritsumeikan Univ.)
(2) VLD	09:55-10:20	Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers	Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
(3) VLD	10:20-10:45	Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer	Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
(4) VLD	10:45-11:10	Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems	Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.)
	11:10-11:25	Break ( 15 min. )
Mon, Jan 24 AM 11:25 - 12:15
(5) CPSY	11:25-11:50	FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation	Kaoru Yamamoto, Takayuki Kawahara (TUS)
(6) VLD	11:50-12:15	Multi-spin-flip method for Ising machines and its application	Tatsuhiko Shirai, Nozomu Tagawa (Waseda Univ.)
	12:15-13:15	Break ( 60 min. )
Mon, Jan 24 PM 13:15 - 14:05
(7) RECONF	13:15-14:05	[Invited Talk] A Challenge of Research, Development, Manufacturing, and Marketing of Quantum Computing Control Systems	Takefumi Miyoshi (QuEL, Inc./e-trees.Japan, Inc./Osaka Univ.)
	14:05-14:25	Break ( 20 min. )
Mon, Jan 24 PM 14:25 - 15:40
(8) CPSY	14:25-14:50		()
(9) RECONF	14:50-15:15	Implementation of a RISC-V SMT Core in Virtual Engine Architecture	Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT)
(10)	15:15-15:40
	15:40-15:55	Break ( 15 min. )
Mon, Jan 24 PM 15:55 - 17:35
(11) RECONF	15:55-16:20	Accelerating Deep Neural Networks on Edge Devices by Knowledge Distillation and Layer Pruning	Yuki Ichikawa, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Titech)
(12) RECONF	16:20-16:45	Addition of DPU Training Function by Tail Layer Training	Yuki Takashima, Akira Jinguji, Hiroki Nakahara (Tokyo Tech)
(13) RECONF	16:45-17:10	A study of an accelerator for CNN inference on FPGA clusters	Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS)
(14) CPSY	17:10-17:35	Ternarizing Deep Spiking Neural Network	Man Wu, Yirong Kan, Van_Tinh Nguyen, Renyuan Zhang, Yasuhiko Nakashima (NAIST)
	17:35-18:00	Break ( 25 min. )
	18:00-20:00	Online Banquet ( 120 min. )
Tue, Jan 25 AM 09:30 - 11:10
(15) CPSY	09:30-09:55	GPU acceleration of algorithm for minimal distance approximate calculation between two objects	Masumi Fukuta, Takakazu Kurokawa, Takashi Matsubara, Keisuke Iwai (NDA)
(16) CPSY	09:55-10:20	An Accuracy-Aware Data Size Reduction Method of 3D Lidar SLAM	Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
(17) RECONF	10:20-10:45	FPGA Implementation of Radar Imaging for Walk-Through Security Screening System	Tatsuya Sumiya, Yuki Kobayashi, Masayuki Ariyoshi (NEC)
(18) RECONF	10:45-11:10	An Implementation of a Real-time Stereo Matching System on FPGA	Kaijie Wei (Keio Univ.), Yuki Kuno (Marelli Corp.), Masatoshi Arai (Saitama Univ.), Hideharu Amano (Keio Univ.)
	11:10-11:25	Break ( 15 min. )
Tue, Jan 25 AM 11:25 - 12:15
(19) CPSY	11:25-11:50	A Light-Weight Machine Learning based Packet Routing using Online Sequential Learning	Kenji Nemoto, Masaki Furukawa, Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.)
(20) CPSY	11:50-12:15
	12:15-13:15	Break ( 60 min. )
Tue, Jan 25 PM 13:15 - 14:30
(21) RECONF	13:15-13:40	A Study on Technology mapping method for Scalable Logic Module	Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.)
(22)	13:40-14:05
(23) RECONF	14:05-14:30	Initial Design and Evaluation of RIKEN CGRA: Data-Driven Architecture for Future HPC	Boma Adhi, Carlos Cortes, Yiyu Tan (R-CCS), Takuya Kojima (Tokyo Univ.), Artur Podobas (KTH), Kentaro Sano (R-CCS)
	14:30-14:45	Break ( 15 min. )
Tue, Jan 25 PM 14:45 - 16:25
(24) RECONF	14:45-15:10	A Preliminary Evaluation of a Compiler for RIKEN CGRA in HPC	Takuya Kojima (U.Tokyo), Carlos Cesar Cortes Torres, Boma Adhi, Yiyu Tan, Kentaro Sano (RIKEN)
(25) RECONF	15:10-15:35
(26) RECONF	15:35-16:00	Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA)	Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT)
(27) RECONF	16:00-16:25	Design of a Quadruple Precision Floating-Point Arithmetic Unit for FPGAs and its Evaluation by Conjugate Gradient Method	Naoki Kakine, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ)
	16:25-16:40	Break ( 15 min. )
Tue, Jan 25 PM 16:40 - 17:30
(28) VLD	16:40-17:05	Testing of Optimization Performance of Android DEX Compilers Based on Native Code Comparison	Naoki Yoshida, Nagisa Ishiura (Kwansei Gakuin Univ.)
(29) CPSY	17:05-17:30	Hard-to-Detect Hardware Trojan Attack Exploiting Coherence Control Mechanisms	Yoshiya Shikama (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)

Announcement for Speakers
General Talk	Each speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Daisuke KANEMOTO (Osaka Univ.) E-: deeieng-u
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
CPSY	Technical Committee on Computer Systems (CPSY) [Latest Schedule]
	Contact Address	CPSY WEB https://www.ieice.org/~cpsy/
RECONF	Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
	Contact Address	Hiroki Nakahara （Tokyo Inst. of Tech.） Yuki Kobayashi （NEC） E-: y-bahqc
	Announcement	http://www.ieice.org/~reconf/
IPSJ-ARC	Special Interest Group on System Architecture (IPSJ-ARC) [Latest Schedule]
	Contact Address
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
	Contact Address	Kenshu Seto (Tokyo City University) E-: ktcu
	Announcement	Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/