Mon, Jan 23 AM 10:30 - 12:10 |
(1) RECONF |
10:30-10:55 |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool |
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) |
(2) RECONF |
10:55-11:20 |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) |
Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) |
(3) RECONF |
11:20-11:45 |
Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder |
Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU) |
(4) RECONF |
11:45-12:10 |
Evaluation of reduced routing resources for HPC-Oriented CGRAs |
Carlos Cortes, Boma Adhi, Tomohiro Ueno (RIKEN Center for Computational Science (R-CCS)), Yiyu Tan (Dept of Systems Innovation Engineering Iwate Univ.), Takuya Kojima (Information Science and Technology The Univ. of Tokyo), Artur Podobas (KTH Royal Inst. of Technology), Kentaro Sato (RIKEN Center for Computational Science (R-CCS)) |
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12:10-13:30 |
Lunch Break ( 80 min. ) |
Mon, Jan 23 PM 13:30 - 14:20 |
(5) RECONF |
13:30-14:20 |
[Invited Talk]
Can we say "No FPGA, No Smart City"?
-- Let's declare if we do a smart city, we need FPGAs. -- |
Hiroaki Nishi (Keio Univ.) |
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14:20-14:40 |
Break ( 20 min. ) |
Mon, Jan 23 PM 14:40 - 15:55 |
(6) |
14:40-15:05 |
(IPSJ-SLDM) |
(7) |
15:05-15:30 |
(IPSJ-SLDM) |
(8) |
15:30-15:55 |
(IPSJ-SLDM) |
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15:55-16:10 |
Break ( 15 min. ) |
Mon, Jan 23 PM 16:10 - 16:50 |
(9) RECONF |
16:10-16:20 |
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(10) RECONF |
16:20-16:30 |
Interface development for Python use of FPGA cluster ESSPER |
Taiki Watanabe (TUT), Kentaro Sano (R-CCS), Yukinori Sato (TUT) |
(11) RECONF |
16:30-16:40 |
A study on optimisation of Back Projection Processing of CT Images using FPGA |
Jumpei Mano, Takaaki Miyajima (Meiji Univ), Peng Chen (AIST), Mohamed Wahib, Kentaro Sano (RIKEN) |
(12) RECONF |
16:40-16:50 |
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16:50-17:10 |
RECONF Award Ceremony ( 20 min. ) |
Tue, Jan 24 AM 10:30 - 12:10 |
(13) VLD |
10:30-10:55 |
Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM |
Motoki Kamibayashi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Masanori Hashimoto (Kyoto Univ.) |
(14) VLD |
10:55-11:20 |
Study on Wireless Transmission Data Reduction Method and Its Implementation in Emotion Recognition System Using Electroencephalogram |
Yuuki Harada, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.) |
(15) VLD |
11:20-11:45 |
Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips |
Chiharu Shiro (Ritsumeiakn Univ.), Hiroki Nishikawa (Osaka Univ.), Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeiakn Univ.) |
(16) VLD |
11:45-12:10 |
Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree |
Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) |
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12:10-13:30 |
Lunch Break ( 80 min. ) |
Tue, Jan 24 PM 13:30 - 15:10 |
(17) RECONF |
13:30-13:55 |
Implementing a quantum computer simulator Qulacs on FPGAs |
Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba) |
(18) RECONF |
13:55-14:20 |
An Implementation of Generic IP-cores for Linux by Using VIRTIO Interface |
Kota Asanuma (TUAT/e-trees), Takefumi Miyoshi (e-trees) |
(19) RECONF |
14:20-14:45 |
Leveraging dynamic parameter for solution search acceleration in bio-inspired hardware SAT solver |
Anh Hoang Ngoc Nguyen (Fujitsu ltd.) |
(20) RECONF |
14:45-15:10 |
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Akinobu Tomori (Univ. Ryukyu), Yasunori Osana (Univ. Ryukyus) |