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=============================================== Technical Committee on Computer Systems (CPSY) Chair: Tsutomu Yoshinaga (Univ. of Electro-Comm.) Vice Chair: Akira Asato (Fujitsu), Yasuhiko Nakajima (NAIST) Secretary: Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Electro-Comm.) Assistant: Hiroaki Inoue (NEC), Takeshi Ohkawa (Utsunomiya Univ.) =============================================== Technical Committee on Dependable Computing (DC) Chair: Nobuyasu Kanekawa (Hitachi) Vice Chair: Michiko Inoue (NAIST) Secretary: Koji Iwata (RTRI), Tatsuhiro Tsuthiya (Osaka Univ.) DATE: Fri, Apr 17, 2015 09:00 - 17:30 PLACE: (http://www.meiji.ac.jp/cip/english/about/campus/nakano.html. Prof. Satoshi Fukumoto. +81-42-585-8437) TOPICS: ---------------------------------------- Fri, Apr 17 AM (09:00 - 10:15) ---------------------------------------- (1) 09:00 - 09:25 Redundant Configuration on FPGA with Rejuvenation for Real Time Applications Aromhack Saysanasongkham, Satoshi Fukumoto (Tokyo Metropolitan Univ.) (2) 09:25 - 09:50 Off-loading to PEACH2 of Gravitational Calculation Chiharu Tsuruta, Takuya Kuhara (Keio univ.), Miki Yohei (Univ. of Tsukuba), Hideharu Amano (Keio univ.) (3) 09:50 - 10:15 A Proposal of Time-Lag-Less n-Fault-Tolerant Control System Hitoshi Iwai ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Apr 17 AM (10:25 - 11:40) ---------------------------------------- (4) 10:25 - 10:50 3D Shared Bus Architecture Using Inductive-Coupling Interconnect Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano (Keio Univ.) (5) 10:50 - 11:15 Design and Implementation of FPGA-based Sorting Accelerator Ryohei Kobayashi, Kenji Kise (Tokyo Tech) (6) 11:15 - 11:40 An IP-NoC Translator for Connecting NoCs and Internet Naoaki Kashiwagi, Hiroki Matsutani (Keio Univ.) ----- Lunch Break ( 80 min. ) ----- ---------------------------------------- Fri, Apr 17 PM (13:00 - 14:40) ---------------------------------------- (7) 13:00 - 13:25 CGRA in Cache for Graph Applications Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) (8) 13:25 - 13:50 A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) (9) 13:50 - 14:15 Near Memory Processing Architecture for High Performance Atypical Applications Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) (10) 14:15 - 14:40 Parallel Processor Architecture based on Small World Connection Hideki Mori (Meiji Univ.), Minoru Uehara, Katsuyoshi Matsumoto (Toyo Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Apr 17 PM (14:50 - 15:40) ---------------------------------------- (11) 14:50 - 15:40 [Special Invited Talk] On Hardware for high-speed pattern matching Tsutomu Sasao (Meiji Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Apr 17 PM (15:50 - 17:30) ---------------------------------------- (12) 15:50 - 16:15 A parallel-operation-oriented FPGA architecture Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) (13) 16:15 - 16:40 A Case Study on Prototyping Cloud based IoT devices Minoru Uehara (Toyo Univ.) (14) 16:40 - 17:05 Frequency Domain aware Power Analysis based on Two Steps Hierarchal Alignment Method Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) (15) 17:05 - 17:30 Prototyping of GPS-based Item Finder System Soichiro Kanagawa, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Mon, May 11, 2015 - Wed, May 13, 2015: Kitakyushu International Conference Center , Topics: LSI and System Workshop 2015 # SECRETARY: Akira ASATO (FUJITSU) TEL +81-44-754-3233, FAX +81-44-754-3214 E-mail: a          === Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Mon, May 11, 2015 - Wed, May 13, 2015: Kitakyushu International Conference Center , Topics: LSI and System Workshop 2015 Tue, Jun 16, 2015: Kikai-Shinko-Kaikan Bldg. [Mon, Apr 27], Topics: Reliable design and Test, etc. Last modified: 2015-04-09 13:40:50 |
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