Thu, Sep 8 AM
09:00 - 10:15 |
| (1) |
09:00-09:25 |
The comparison of electrical characteristics of FCBGA packaging substrate based on MLTS and conventional build-up PWB |
Jun Sakai, Koichiro Nakase (NEC), Hirokazu Honda (NECエレクトロニクス), Hirobumi Inoue (NEC) |
| (2) |
09:25-09:50 |
Characteristic dielectric constant for polyimide thin films at 10GHz |
Shigemasa Segawa (PI R&D), Sachiko Ito, Katsuya Kikuchi, Kazuhiko Tokoro, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) |
| (3) |
09:50-10:15 |
Development of Design Techniques for Semiconductor-Package By using Simplified DRAM Macro Model of Power System |
Satoshi Nakamura, Takashi Suga (Hitachi PERL), Mitsuaki Katagiri, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose, イサ サトシ (Elpida) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Thu, Sep 8 AM
10:30 - 11:45 |
| (4) |
10:30-10:55 |
Performance evaluation of high-precision manipulator for probing on entire chip surface |
Akira Nakada, Keijiro Itakura, Hiroshi Kubota (Kumamoto Univ.) |
| (5) |
10:55-11:20 |
Visualization of High Frequency Electromagnetic Field over Fine Circuits by Magnetooptic/Electrooptic Probe |
Mizuki Iwanami, Shigeki Hoshino, Norio Masuda (NEC), Masato Kishi (Univ. of Tokyo), Masahiro Tsuchiya (NICT) |
| (6) |
11:20-11:45 |
Diagnostic Test Compaction for Combinational and Sequential Circuits |
Yoshinobu Higami (Ehime Univ.), Kewal K Saluja (Univ. of Wisconsin), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ.) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Sep 8 PM
13:00 - 14:15 |
| (7) |
13:00-13:25 |
System Packaging Issue and Solution of Renesas SiP |
Noriaki Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, Takashi Akazawa (ルネサステクノロジ) |
| (8) |
13:25-13:50 |
Basic Study of Proper Circuit Line Structure for Advanced System in Package |
Shouhei Yasuda (Melco Display Tech.), Yoshiharu Iwata, Ryohei Satoh (Osaka Univ.) |
| (9) |
13:50-14:15 |
The Study of Silicon Stress for Stacked Die Packages |
Kenji Abe, Eiichi Yamada, Yutaka Suzuki, Masazumi Amagai (TI Japan) |
| |
14:15-14:30 |
Break ( 15 min. ) |
Thu, Sep 8 PM
14:30 - 16:10 |
| (10) |
14:30-14:55 |
The Study of Stress Sensor for Stacked Die Packages |
Yutaka Suzuki, Kenji Abe, Eiichi Yamada, , Masazumi Amagai (TI Japan) |
| (11) |
14:55-15:20 |
Design and fabrication of MOS devices patterning with LCD image projection |
Akira Nakada, Satoshi Wakimoto, Hiroshi Kubota (Kumamoto Univ.) |
| (12) |
15:20-15:45 |
2 GHz Linear Amplifier Module with Feedforward Linearizer |
Hiroyuki Kayano (Toshiba), Yuji Ohtsuka, Masao Suzuki, Masaya Ishiguro (TDMS), Tatsunori Hashimoto (Toshiba) |
| (13) |
15:45-16:10 |
A CMOS Impulse Radio Ultra-Wideband Transceiver for 1Mb/s Data Communications and ±2.5cm Range Findings |
Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda (Keio Univ.) |
Fri, Sep 9 AM
09:00 - 10:40 |
| (14) |
09:00-09:50 |
[Invited Talk]
The study of the high frequency electrical characteristics in high-speed digital device mounting |
Chihiro Ueda (AETJAPAN) |
| (15) |
09:50-10:15 |
Analysis of Transmission Characteristic of High-speed Differential Sgnal Bus |
Tsuyoshi Tokiwa, Toshio Sudo (Toshiba), Nobuhiro Tsuruta (Toshiba DME), Yoshihiro Nishida (Toshiba DM) |
| (16) |
10:15-10:40 |
Measuemnt and Discussion of Degradation of Pulse Feature according with Line Length Increase |
Koichi Yabuuchi (EMtech), Tamotsu Usami, Yutaka Akiyama, Kanji Otsuka (Meisei Univ.) |
| |
10:40-10:55 |
Break ( 15 min. ) |
Fri, Sep 9 AM
10:55 - 11:45 |
| (17) |
10:55-11:20 |
Lead-free bumping and its process integrity for fine pitch interconnects |
Hirokazu Ezawa, Masaharu Seto, Kazuhito Higuchi (Toshiba) |
| (18) |
11:20-11:45 |
Development of New Surface Finish Technology for Package Substrates with Excellent Bondability |
Kiyotaka Tsukada (IBIDEN) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Fri, Sep 9 PM
13:00 - 14:15 |
| (19) |
13:00-13:25 |
Simultaneous switching noise(SSN) and EMI of a semiconductor package |
Takanobu Kushihira (MSC), Toshio Sudo (TSB) |
| (20) |
13:25-13:50 |
Study of 6Gbps Operation on 0.18um Node CMOS I/O Inverter with Transmission Structure in Signal and Power Distribution Lines |
Yutaka Akiyama (Meisei Univ.), Tsuneo Ito (Excel Service), Kyouji Ito (Renesas NJS), Kanji Otsuka (Meisei Univ.) |
| (21) |
13:50-14:15 |
Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG |
Masaharu Yamamoto (STARC), Yayoi Hayasi, Hitoshi Endo (Hitachi ULSI), Hiroo Masuda (STARC) |
| |
14:15-14:30 |
Break ( 15 min. ) |
Fri, Sep 9 PM
14:30 - 15:20 |
| (22) |
14:30-15:20 |
[Invited Talk]
On chip transmission line interconnect |
Kazuya Masu, Kenichi Okada, Hiroyuki Ito (Tokyo Institute of Technology) |
| |
15:20-15:30 |
Break ( 10 min. ) |
Fri, Sep 9 PM
15:30 - 17:00 |
| (23) |
15:30-17:00 |
[Panel Discussion] |
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