IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Kota Nakajima (Fujitsu Lab.)
Vice Chair Yasushi Inoguchi (JAIST), Tomoaki Tsumura (Nagoya Inst. of Tech.)
Secretary Ryohei Kobayashi (Univ. of Tsukuba), Shugo Ogawa (Hitachi)
Assistant Ryuichi Sakamoto (Tokyo Inst. of Tech.), Takumi Honda (Fujitsu)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]

Special Interest Group on High Performance Computing (IPSJ-HPC) [schedule] [select]
Chair Takahiro Katagiri
Secretary Hiroyuki Takizawa, Rio Yokota, Masahiro Nakao, Kohta Nakashima, Kazuhiko Komatsu

Conference Date Tue, Dec 5, 2023 09:00 - 21:00
Wed, Dec 6, 2023 09:00 - 19:05
Topics Computer Systems, HPC, etc. 
Conference Place Okinawa Industry Support Center 
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on CPSY.

Tue, Dec 5 AM 
09:00 - 09:05
  -  
Tue, Dec 5 AM 
09:05 - 10:20
(1) 09:05-09:30  
(2) 09:30-09:55  
(3) 09:55-10:20  
  10:20-10:30 Break ( 10 min. )
Tue, Dec 5 PM 
10:30 - 12:10
(4) 10:30-10:55  
(5)
CPSY
10:55-11:20 Performance improvements of Multi-Platform Parallel Computing System Based on Web Technologies Soki Imaizumi, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
(6)
CPSY
11:20-11:45 A Performance Evaluation of Job Switching for Interactive High-Performance Computing Koki Kusunoki, Jun Kato, Masahiro Miwa (Fujitsu)
(7) 11:45-12:10  
  12:10-13:10 ( 60 min. )
Tue, Dec 5 PM 
13:10 - 14:50
(8) 13:10-13:35  
(9) 13:35-14:00  
(10) 14:00-14:25  
(11)
CPSY
14:25-14:50 Design of Resettable and Non-Destructive Readable TFF for Half-Flux-Quantum Circuits Yuki Matsumoto (Kyushu Univ.), Toranosuke Nakayama, Shoma Tanemura, Masamitsu Tanaka (Nagoya Univ.), Takatsugu Ono (Kyushu Univ.)
  14:50-15:00 Break ( 10 min. )
Tue, Dec 5 PM 
15:00 - 16:40
(12) 15:00-15:25  
(13) 15:25-15:50  
(14) 15:50-16:15  
(15)
CPSY
16:15-16:40 Implementation of a mixed cluster system using Android OS and Linux OS Yusaku Terashima, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
  16:40-16:50 Break ( 10 min. )
Tue, Dec 5 PM 
16:50 - 18:05
(16) 16:50-17:15  
(17) 17:15-17:40  
(18)
CPSY
17:40-18:05 Evaluation of conversion overheads for the sparse matrix format appliying indices of the non-zero elements dictionary compression to accelerate SpMV on GPU Shun Murakami (JAIST), Kazunori Yoneda, Iwamura Takashi, Masahiro Watanabe (Fujitsu Japan), Yasushi Inoguchi (JAIST)
Tue, Dec 5 PM 
19:00 - 21:00
  -  
Wed, Dec 6 AM 
09:00 - 09:05
  -  
Wed, Dec 6 AM 
09:05 - 10:20
(19) 09:05-09:30  
(20) 09:30-09:55  
(21) 09:55-10:20  
  10:20-10:30 Break ( 10 min. )
Wed, Dec 6 PM 
10:30 - 12:10
(22)
CPSY
10:30-10:55 Development of Genetic Algorithm for Grid Graph in Order/Degree Problem Kimura Hiroto, Yoshiko Hanada (Kansai Univ.), Masahiro Nakao, Keiji Yamamoto (R-CCS)
(23)
CPSY
10:55-11:20
(24)
CPSY
11:20-11:45
(25)
CPSY
11:45-12:10 An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
  12:10-13:10 ( 60 min. )
Wed, Dec 6 PM 
13:10 - 14:50
(26) 13:10-13:35  
(27) 13:35-14:00  
(28)
CPSY
14:00-14:25 Prototype development and preliminary evaluation of a multi-level pipeline CGRA Tomoya Akabe, Yasuhiko Nakashima (NAIST)
(29) 14:25-14:50  
  14:50-15:00 Break ( 10 min. )
Wed, Dec 6 PM 
15:00 - 16:15
(30) 15:00-15:25  
(31) 15:25-15:50  
(32) 15:50-16:15  
  16:15-16:25 Break ( 10 min. )
Wed, Dec 6 PM 
16:25 - 17:40
(33) 16:25-16:50  
(34) 16:50-17:15  
(35)
CPSY
17:15-17:40 An Efficient Sparse Matrix Storage Format for Sparse Matrix-Vector Multiplication and Sparse Matrix-Transpose-Vector Multiplication on GPUs Ryohei Izawa, Yasushi Inoguchi (JAIST)
  17:40-17:50 Break ( 10 min. )
Wed, Dec 6 PM 
17:50 - 19:05
(36) 17:50-18:15  
(37) 18:15-18:40  
(38) 18:40-19:05  

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address  
Announcement CPSY WEB
https://www.ieice.org/~cpsy/
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-HPC Special Interest Group on High Performance Computing (IPSJ-HPC)   [Latest Schedule]
Contact Address  


Last modified: 2023-10-30 09:25:48


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to CPSY Schedule Page]   /   [Return to IPSJ-ARC Schedule Page]   /   [Return to IPSJ-HPC Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan