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Technical Committee on Computer Systems (CPSY) (Searched in: 2016)
Search Results: Keywords 'from:2017-01-23 to:2017-01-23'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 13:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A Hardware Acceleration of Template Matching using FPGA and MPU Yuji Matumoto, Youichi Tomioka, Junji Kitamichi (The University of Aizu)  VLD2016-70 CPSY2016-106 RECONF2016-51 |
[more] | VLD2016-70 CPSY2016-106 RECONF2016-51 pp.1-6 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 13:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) VLD2016-71 CPSY2016-107 RECONF2016-52 |
Evolutionary algorithms such as Genetic Algorithm (GA) are applied to the optimum design of digital filters. In generall... [more] | VLD2016-71 CPSY2016-107 RECONF2016-52 pp.7-12 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 13:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Keigo Nitadori (RIKEN/AICS) VLD2016-72 CPSY2016-108 RECONF2016-53 |
We have been developing GRAPE9-MPX which is a dedicated system to accelerate the computation with multi precision arithm... [more] | VLD2016-72 CPSY2016-108 RECONF2016-53 pp.13-18 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 14:30 |
Kanagawa | Hiyoshi Campus, Keio Univ. | VLD2016-73 CPSY2016-109 RECONF2016-54 |
[more] | VLD2016-73 CPSY2016-109 RECONF2016-54 pp.19-23 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 14:55 |
Kanagawa | Hiyoshi Campus, Keio Univ. | VLD2016-74 CPSY2016-110 RECONF2016-55 |
[more] | VLD2016-74 CPSY2016-110 RECONF2016-55 pp.25-29 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 15:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2016-75 CPSY2016-111 RECONF2016-56 |
We propose a multiple FPGA system using high speed optical serial interconnection for a inter-connection of FPGAs. In th... [more] | VLD2016-75 CPSY2016-111 RECONF2016-56 pp.31-36 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 15:45 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes Kousuke Tada, Naoto Kawahara, Masato Yoshimi, Celimuge, Wu., Tsutomu Yoshinaga (UEC) VLD2016-76 CPSY2016-112 RECONF2016-57 |
This paper proposes an FPGA-based Handshake join acceleration using multiple-FPGA boards. The proposed multi-node exten... [more] |
VLD2016-76 CPSY2016-112 RECONF2016-57 pp.37-42 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 16:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A Case for FPGA Based 10GbE Switch Aggregating Computation Results of GPUs Kazuma Takemoto, Ami Hayashi, Shin Morishima, Hiroki Matsutani (Keio Univ.) VLD2016-77 CPSY2016-113 RECONF2016-58 |
(To be available after the conference date) [more] | VLD2016-77 CPSY2016-113 RECONF2016-58 pp.43-48 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 16:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | VLD2016-78 CPSY2016-114 RECONF2016-59 |
(To be available after the conference date) [more] | VLD2016-78 CPSY2016-114 RECONF2016-59 pp.49-54 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 17:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Kazusa Musha (Keio Univ.), Tomohiro Kudoh (Tokyo Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2016-90 CPSY2016-126 RECONF2016-71 |
(To be available after the conference date) [more] | VLD2016-90 CPSY2016-126 RECONF2016-71 pp.135-140 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 09:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2016-80 CPSY2016-116 RECONF2016-61 |
[more] | VLD2016-80 CPSY2016-116 RECONF2016-61 pp.61-66 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 09:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Framework for a Hybrid System with a pair of MCU and FPGA Ryota Suzuki, Nakajo Hironori (TUAT) VLD2016-81 CPSY2016-117 RECONF2016-62 |
Recently, FPGAs for mobile use which have low pin count and small packages are commonly available. Due to limitation of... [more] |
VLD2016-81 CPSY2016-117 RECONF2016-62 pp.67-72 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 10:55 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A Case for Remote GPU Assignment for VR Applications Shin Morishima, Masahiro Okazaki (Keio Univ.), Hiroki Matsutani (Keio Univ.PRESTO/NII) VLD2016-82 CPSY2016-118 RECONF2016-63 |
(To be available after the conference date) [more] | VLD2016-82 CPSY2016-118 RECONF2016-63 pp.85-90 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 11:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Evaluation of the PEACH3 used for communication in application Takahiro Kaneda (Keio Univ.), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ.) VLD2016-83 CPSY2016-119 RECONF2016-64 |
Tightly Coupled Accelerators(TCA) architecture connects a number of GPUs directly through PCI Express using dedicated sw... [more] | VLD2016-83 CPSY2016-119 RECONF2016-64 pp.91-96 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 11:45 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Optimization of Fresnel hologram computation on GPU using decomposition method Shinpei Watanabe (Utsunomiya Univ.), Boaz Jessie Jackin (NICT), Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai, Takanobu Baba (Utsunomiya Univ.) VLD2016-84 CPSY2016-120 RECONF2016-65 |
Computer generated hologram (CGH) is a hopeful technology for realizing 3D displays. CGH has an advantage that it does n... [more] | VLD2016-84 CPSY2016-120 RECONF2016-65 pp.97-102 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 13:30 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.) VLD2016-85 CPSY2016-121 RECONF2016-66 |
Recently, heterogeneous multi-core processer is spreading. We should exactly understand both static and dynamic behavio... [more] |
VLD2016-85 CPSY2016-121 RECONF2016-66 pp.103-108 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 13:55 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Expression of Positional registers for Tamper resistance Kiyohiro Sato, Naoki Fujieda, Shuichi Ichikawa (TUT) VLD2016-86 CPSY2016-122 RECONF2016-67 |
[more] | VLD2016-86 CPSY2016-122 RECONF2016-67 pp.109-114 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 14:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) VLD2016-87 CPSY2016-123 RECONF2016-68 |
Such sensor network applicatio, which is one of core technologies in IoT, are requesting a change for consuming energy o... [more] | VLD2016-87 CPSY2016-123 RECONF2016-68 pp.115-120 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 15:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement Haruyoshi Yonekawa, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido Univ.) VLD2016-88 CPSY2016-124 RECONF2016-69 |
[more] | VLD2016-88 CPSY2016-124 RECONF2016-69 pp.127-132 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 15:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization Tomoya Fujii, Simpei Sato, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido univ.) VLD2016-79 CPSY2016-115 RECONF2016-60 |
For a pre-trained deep convolutional neural network (CNN) aim at an embedded system, a high-speed and a low power consum... [more] | VLD2016-79 CPSY2016-115 RECONF2016-60 pp.55-60 |
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