Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2018-04-19 10:10 |
Tokyo |
|
Reliability Enhancement Technique with Horizontal Error Detection and Vertical-LDPC in 3D-TLC NAND Flash Memories Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi (Chuo Univ.) ICD2018-1 |
Conventional Asymmetric Coding (AC) has been proposed for improving NAND flash memories. In this work, Horizontal Error ... [more] |
ICD2018-1 pp.1-6 |
ICD |
2018-04-19 10:35 |
Tokyo |
|
Application-optimized heterogeneously-integrated storage with non-volatile memories Chihiro Matsui, Ken Takeuchi (Chuo Univ.) ICD2018-2 |
Data center storages require application-optimized heterogeneous integration of non-volatile memories. Two types of stor... [more] |
ICD2018-2 pp.7-10 |
ICD |
2018-04-19 11:00 |
Tokyo |
|
[Invited Talk]
Data-aware Computing with Highly Reliable SSD System Ken Takeuchi (Chuo Univ.) ICD2018-3 |
[more] |
ICD2018-3 p.11 |
ICD |
2018-04-19 13:00 |
Tokyo |
|
[Invited Talk]
VLSI implementation of chaotic Boltzmann machine for deep learning hardware Takashi Morie, Masatoshi Yamaguchi, Ichiro Kawashima, Hakaru Tamukoh (Kyushu Inst. of Tech.) ICD2018-4 |
The Boltzmann machine (BM) model has been proposed as an optimization-problem solver as well as a learning machine using... [more] |
ICD2018-4 p.13 |
ICD |
2018-04-19 13:50 |
Tokyo |
|
[Invited Talk]
Hard- and Soft- Synchronized Developments of Resistive Analog Neuro Devices and Systems Hiroyuki Akinaga, Hisashi Shima, Yasuhisa Naitoh (AIST), Tetsuya Asai (Hokkaido Univ.) ICD2018-5 |
Artificial Neural Network (ANN) System for Inference has attracted increasing attention. As widely known, Resistive Ana... [more] |
ICD2018-5 p.15 |
ICD |
2018-04-19 14:55 |
Tokyo |
|
[Invited Talk]
Low power Deep Learning hardware using emerging analog non-volatile memory Irina Kataeva (DENSO Corp.) |
In recent years, Artificial Intelligence, Deep Learning in particular, has become a hot topic of both research and pract... [more] |
|
ICD |
2018-04-19 15:45 |
Tokyo |
|
[Invited Talk]
Introduction of the Latest GPU Technology for AI
-- How to deal with the DDR Memory Band Width Slow Improvement -- Toru Baji (NVIDIA) |
(To be available after the conference date) [more] |
|
ICD |
2018-04-19 16:35 |
Tokyo |
|
[Invited Talk]
Problem solving of artificial intelligence with the Memorism processor Katsumi Inoue (AOT), Pham Cong-Kha (UEC) ICD2018-6 |
[more] |
ICD2018-6 pp.17-22 |
ICD |
2018-04-20 09:55 |
Tokyo |
|
[Invited Lecture]
A new core transistor equipped with NVM functionality without using any emerging memory materials Yasuhiro Taniguchi, Shoji Yoshida, Owada Fukuo, Yutaka Shinagawa, Hideo Kasai (Floadia), Lin Jia You, Wei I Huan (PTC), Daisuke Okada, Koichi Nagasawa, Kosuke Okuyama (Floadia) ICD2018-7 |
A tri-gate core transistor which has nonvolatile memory [NVM] functionality in midsection of a logic transistor gate was... [more] |
ICD2018-7 pp.23-27 |
ICD |
2018-04-20 10:20 |
Tokyo |
|
[Invited Lecture]
An Implementation of 2RW Dual-Port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT Yohei Sawada, Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Makoto Yabuuchi (REL), Yoshihiro Shinozaki, Kyoji Ito (NSW), Shinji Tanaka, Nii Koji, Shiro Kamohara (REL) ICD2018-8 |
[more] |
ICD2018-8 pp.29-32 |
ICD |
2018-04-20 10:45 |
Tokyo |
|
[Invited Lecture]
A Dynamic Power Reduction in Synchronous 2RW 8T Dual-Port SRAM by Adjusting Wordline Pulse Timing with Same/Different Row Access Mode Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii (REL) ICD2018-9 |
(To be available after the conference date) [more] |
ICD2018-9 pp.33-38 |
ICD |
2018-04-20 11:10 |
Tokyo |
|
[Invited Talk]
A 512Gb 3b/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Toshifumi Hashimoto (TMC), Hao Nguyen, Ken Cheah, Hiroshi Sugawara, Seungpil Lee (WDC), Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura (TMC) ICD2018-10 |
A 512Gb 3b/cell flash has been developed on a 96-WL-layer BiCS FLASH technology. This work implements three key technolo... [more] |
ICD2018-10 pp.39-44 |
ICD |
2018-04-20 13:00 |
Tokyo |
|
[Invited Talk]
Random Circuits for Information Security Hirofumi Shinohara (Waseda Univ.) ICD2018-11 |
[more] |
ICD2018-11 p.45 |
ICD |
2018-04-20 13:50 |
Tokyo |
|
[Invited Talk]
Memory LSI using crystalline oxide semiconductor FET Jun Koyama, Takako Seki, Yuto Yakubo, Satoru Ohshita, Kazuma Furutani, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda (SEL), Masahiro Fujita (The Univ. of Tokyo), Shunpei Yamazaki (SEL) ICD2018-12 |
FETs fabricated with a c-axis aligned crystalline In-Ga-Zn oxide semiconductor (CAAC-IGZO) have an extremely low off-sta... [more] |
ICD2018-12 pp.47-52 |
ICD |
2018-04-20 14:55 |
Tokyo |
|
[Invited Talk]
Design and Development of a memory-based reconfigurable logic device Mamoru Ohara (TIRI), Masayuki Sato (TRL), Tadashi Okabe (TIRI), Mitsunori Katsu (TRL) ICD2018-13 |
[more] |
ICD2018-13 pp.53-54 |