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Technical Committee on Reconfigurable Systems (RECONF)  (Searched in: 2014)

Search Results: Keywords 'from:2014-06-11 to:2014-06-11'

[Go to Official RECONF Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 16 of 16  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2014-06-11
17:00
Miyagi Katahira Sakura Hall [Invited Talk] Prospects of Custom Accelerators for Large-Scale Computation -- Perspectives of Applications, Architectures, and Circuits --
Masanori Hariyama (Tohoku Univ.) RECONF2014-1
 [more] RECONF2014-1
pp.1-4
RECONF 2014-06-12
09:00
Miyagi Katahira Sakura Hall A Dynamic Reconfigurable Mixed Analog-Digital Filter -- Applied to an Acoustic Diagnostic --
Hiroki Nakahara, Hideki Yoshida (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Renji Mikami (Mikami Consul.) RECONF2014-2
A cochlear filter bank for an audio band is used for an acoustic diagnostic,
which detects broken points of a wall.
H... [more]
RECONF2014-2
pp.5-10
RECONF 2014-06-12
09:25
Miyagi Katahira Sakura Hall Optimized HOG for database system
Mao Hatto, Takaaki Miyajima, Hiroki Matsutani, Hideharu Amano (Keio Univ.) RECONF2014-3
As technology of High Performance Computing and Pattern Recognition has evolved rapidly, Human
Detection system also ha... [more]
RECONF2014-3
pp.11-16
RECONF 2014-06-12
09:50
Miyagi Katahira Sakura Hall Highly-Parallel FPGA Accelerator for DNA Sequence Alignment Using the Burrows-Wheeler Algorithm
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-4
The mapping of millions of short DNA fragments to a large genome is a very important aspect of the modern bioinformatics... [more] RECONF2014-4
pp.17-20
RECONF 2014-06-12
10:25
Miyagi Katahira Sakura Hall Improvement of Implementability by Exploring Routing Architecture in Flex Power FPGA
Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Hanpei Koike (AIST) RECONF2014-5
(To be available after the conference date) [more] RECONF2014-5
pp.21-25
RECONF 2014-06-12
10:50
Miyagi Katahira Sakura Hall An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] RECONF2014-6
pp.27-30
RECONF 2014-06-12
11:15
Miyagi Katahira Sakura Hall Three-dimensional FPGA Structure using High-speed Serial Communication
Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-7
The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integra... [more] RECONF2014-7
pp.31-36
RECONF 2014-06-12
11:40
Miyagi Katahira Sakura Hall Body bias control of low-power reconfigurable accelerator CMA-SOTB
Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.) RECONF2014-8
For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator cal... [more] RECONF2014-8
pp.37-42
RECONF 2014-06-12
13:45
Miyagi Katahira Sakura Hall A Design of Blokus Player Algorithm with Impulse High-Level Synthesis Tools
Ryo Kawai, Tomonori Izumi (Ritsumeikan Univ.) RECONF2014-9
 [more] RECONF2014-9
pp.43-47
RECONF 2014-06-12
14:10
Miyagi Katahira Sakura Hall Zyndroid: HW/SW Coprocessing Platform for Android Applications
Susumu Mashimo, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-10
Nowadays, high performance of Android systems is required because the embedded systems are used in several fields and th... [more] RECONF2014-10
pp.49-54
RECONF 2014-06-12
14:35
Miyagi Katahira Sakura Hall A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis
Koji Okina, Rie Soejima, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2014-11
 [more] RECONF2014-11
pp.55-60
RECONF 2014-06-12
15:00
Miyagi Katahira Sakura Hall A Study on Accelerating Image Recognition Processing by HW/SW Cooperative Processing on an FPGA for Automatic Watch System on Navigation
Takeshi Ohkawa (Utsunomiya Univ.), Yohei Matsumoto (Tokyo Marine Univ.), Daichi Uetake, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) RECONF2014-12
Accidents on vessel traffic are mainly caused by human error of deficient watching. It is expected to raise the safety o... [more] RECONF2014-12
pp.61-66
RECONF 2014-06-12
15:35
Miyagi Katahira Sakura Hall Implementation of a RISC Processor with a Complex Instruction Accelerator -- Return to a CISC --
Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) RECONF2014-13
In this paper, we propose a RISC processor with an accelerator which can execute a complex instruction
with a co-proces... [more]
RECONF2014-13
pp.67-72
RECONF 2014-06-12
16:00
Miyagi Katahira Sakura Hall FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache
Kenji Kanazawa, Tsutomu Maruyama (Univ. of Tsukuba) RECONF2014-14
WalkSAT (WSAT) is one of the stochastic local search algorithms for Boolean Satisfiability (SAT) and Maximum Boolean Sat... [more] RECONF2014-14
pp.73-78
RECONF 2014-06-12
16:25
Miyagi Katahira Sakura Hall Design of an FPGA-Based Accelerator for Shortest-Path Search over Large-Scale Graphs
Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-15
Shortest-path search over large scale graphs plays an important role in various applications. However, shortest path alg... [more] RECONF2014-15
pp.79-83
RECONF 2014-06-12
16:50
Miyagi Katahira Sakura Hall A software processor core with variable parallel execution
Takuya Nagashima, Shoji Tanabe, Yoshiki Yamaguchi (Univ. of Tsukuba) RECONF2014-16
 [more] RECONF2014-16
pp.85-90
 Results 1 - 16 of 16  /   
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