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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2016)
Search Results: Keywords 'from:2017-03-01 to:2017-03-01'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT)  VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| VLD | 2017-03-01 14:25 |
Okinawa | Okinawa Seinen Kaikan | A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-103 |
This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVF... [more] | VLD2016-103 pp.7-12 |
| VLD | 2017-03-01 14:50 |
Okinawa | Okinawa Seinen Kaikan | Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104 |
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] | VLD2016-104 pp.13-18 |
| VLD | 2017-03-01 15:30 |
Okinawa | Okinawa Seinen Kaikan | High accuracy 8*8 approximate multiplier based on OR operation Yi Guo, Heming Sun, Canran Jin, Shinji Kimura (Waseda Univ.) VLD2016-105 |
Approximate computing is a promising approach for error-tolerate applications. Multipliers contribute more area and dela... [more] | VLD2016-105 pp.19-24 |
| VLD | 2017-03-01 15:55 |
Okinawa | Okinawa Seinen Kaikan | A Design Technique for Approximate Circuits based on Artificial Neural Network Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-106 |
This paper proposes a design technique for approximate circuits based on artificial neural network, and then evaluates t... [more] | VLD2016-106 pp.25-30 |
| VLD | 2017-03-01 16:20 |
Okinawa | Okinawa Seinen Kaikan | Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models Shogo Senba, Hiroshi Saito (UoA) VLD2016-107 |
This paper proposes a transformation tool that generates an asynchronous Register Transfer Level (RTL) model with bundle... [more] | VLD2016-107 pp.31-36 |
| VLD | 2017-03-02 09:00 |
Okinawa | Okinawa Seinen Kaikan | Generation of Optimum Screening Patterns for a Screening Circuit to Detect Network Intrusion Tomoaki Hashimoto, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2016-108 |
In our previous study, we proposed a dedicated circuit, called a screening circuit, that screens packes on a network at ... [more] | VLD2016-108 pp.37-42 |
| VLD | 2017-03-02 09:25 |
Okinawa | Okinawa Seinen Kaikan | FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration Naoyuki Miyagawa, Tomoya Kimura, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2016-109 |
In this paper, we propose Fishbone-in-Cage Capacitor (FiCC) that is a new variant of metal fringe capacitor (MFC), and s... [more] | VLD2016-109 pp.43-47 |
| VLD | 2017-03-02 09:50 |
Okinawa | Okinawa Seinen Kaikan | Reliability enhancement of Hierarchical data reading circuit of Wafer scale mask ROM Takaaki Yokoyama, Ochi Hiroyuki (Ritsumeikan Univ) VLD2016-110 |
In the national libraries of developed countries, there is a demand to store large amounts of data in a digital form ove... [more] | VLD2016-110 pp.49-54 |
| VLD | 2017-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-111 |
[more] | VLD2016-111 pp.55-60 |
| VLD | 2017-03-02 10:55 |
Okinawa | Okinawa Seinen Kaikan | Acceleration of a Hotspot Detection Method Based on Approximate String Matching for LSI Mask Pattern Using Table Reference Shuma Tamagawa, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hirohima City Univ.) VLD2016-112 |
In nanoscale LSI fabrication, there exists a pattern on the mask pattern, called a hotspot, which leads to a failure. H... [more] |
VLD2016-112 pp.61-66 |
| VLD | 2017-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-113 |
In current semiconductor design, high quality and short time design is required. In an advanced lithography technology... [more] |
VLD2016-113 pp.67-72 |
| VLD | 2017-03-02 11:45 |
Okinawa | Okinawa Seinen Kaikan | Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2016-114 |
In printed circuit board, to meet requirements such as delay and noise, routing of each net is necessary to achieve its... [more] |
VLD2016-114 pp.73-78 |
| VLD | 2017-03-02 13:30 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) VLD2016-115 |
CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more] | VLD2016-115 p.79 |
| VLD | 2017-03-02 13:55 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
IP Timing Constraints Promotion Challenges
-- A method to automatically generate SoC Timing Constraints -- Tatsuya Nakae, Ichiro Shiihara (Socionext) VLD2016-116 |
It is common that recent SoC is integrated with more than 10 functional IPs which are not only in-house designs but also... [more] | VLD2016-116 p.81 |
| VLD | 2017-03-02 14:20 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
Fast Monte Carlo based timing yield calculation via line sampling Hiromitsu Awano (UTokyo), Takashi Sato (Kyoto Univ.) VLD2016-117 |
[more] | VLD2016-117 pp.83-84 |
| VLD | 2017-03-02 15:00 |
Okinawa | Okinawa Seinen Kaikan | Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118 |
The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order t... [more] | VLD2016-118 pp.85-90 |
| VLD | 2017-03-02 15:25 |
Okinawa | Okinawa Seinen Kaikan | Optimum Temperature Dependent Timing Skew for Temperature Aware Design Makoto Soga, Mineo Kaneko (JAIST) VLD2016-119 |
Electric devices equipping LSIs are widely distributed everywhere on the earth and the space, and LSIs are demanded to o... [more] | VLD2016-119 pp.91-96 |
| VLD | 2017-03-02 15:50 |
Okinawa | Okinawa Seinen Kaikan | MILP Approach to Skew-Aware High Level Synthesis Kai Shimura, Mineo Kaneko (JAIST) VLD2016-120 |
Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed. However, when we tr... [more] |
VLD2016-120 pp.97-102 |
| VLD | 2017-03-02 16:15 |
Okinawa | Okinawa Seinen Kaikan | An algorithm to compute covariance for finding distribution of the maximum Daiki Azuma, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.), Takashi Kambe (Kinki Univ.) VLD2016-121 |
In statistical approaches such as statistical static timing analysis, the distribution of the maximum of plural distribu... [more] | VLD2016-121 pp.103-108 |
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