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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2007)
Search Results: Keywords 'from:2007-05-10 to:2007-05-10'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, IPSJ-SLDM | 2007-05-10 13:30 |
Kyoto | Kyodai Kaikan | Memory Assignment Method for Matrix Processing Array Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas)  VLD2007-1 |
MTA (MaTrix processing Array), which is developed by Renesas Technology Corp., can achieve high performance for digital ... [more] | VLD2007-1 pp.1-6 |
| VLD, IPSJ-SLDM | 2007-05-10 13:55 |
Kyoto | Kyodai Kaikan | Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
Partial forwarding is a design method to put forwarding paths on a part of processor pipeline. To schedule instructions... [more] |
VLD2007-2 pp.7-12 |
| VLD, IPSJ-SLDM | 2007-05-10 14:20 |
Kyoto | Kyodai Kaikan | Reconfigurable Architecture with Caluculation Function for Shift Keying Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2007-3 |
[more] | VLD2007-3 pp.13-18 |
| VLD, IPSJ-SLDM | 2007-05-10 14:55 |
Kyoto | Kyodai Kaikan | A Modeling of Dynamically Reconfigurable Processor using SystemC Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
Recently, dynamically reconfigurable processors (DRPs) based on FPGA technology are proposed. DRPs are implemented on... [more] |
VLD2007-4 pp.19-24 |
| VLD, IPSJ-SLDM | 2007-05-10 15:20 |
Kyoto | Kyodai Kaikan | An Architecture Design and its Evaluation for Speech Recognition System Joh Hashimato, Makoto Saitsuji, Takashi Kambe (Kinki Univ.) VLD2007-5 |
Speech recognition is becoming a popular technology for the implementation of human interfaces. However, conventional ap... [more] | VLD2007-5 pp.25-30 |
| VLD, IPSJ-SLDM | 2007-05-10 16:00 |
Kyoto | Kyodai Kaikan | [Panel Discussion]
Highlevel synthesis; will it be useful or useless? Masahiro Fukui (Ritsumeikan Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Tomonori Izumi (Ritsumeikan Univ.), Akihisa Yamada (SHARP) VLD2007-6 |
As to utilizing high-level synthesis tools effectively, we plan to discuss from the views of LSI designers, high-level s... [more] | VLD2007-6 p.31 |
| VLD, IPSJ-SLDM | 2007-05-11 09:30 |
Kyoto | Kyodai Kaikan | Automatic Generation of a Verification Environment for Hardware Units
-- Application to a Bus Bridge Design -- Rafael Kazumiti Morizawa, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs.) VLD2007-7 |
The verification cost of complex SoCs has been increasing in a fast pace. Many techniques and methodologies have been de... [more] | VLD2007-7 pp.1-6 |
| VLD, IPSJ-SLDM | 2007-05-11 09:55 |
Kyoto | Kyodai Kaikan | On a lower bound for DAG covering problem and its application to an exact algorithm Yusuke Matsunaga (Kyushu Univ.) VLD2007-8 |
[more] | VLD2007-8 pp.7-12 |
| VLD, IPSJ-SLDM | 2007-05-11 10:20 |
Kyoto | Kyodai Kaikan | A Clock Deskew Method using PDE with Discrete Delay Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2007-9 |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2007-9 pp.13-18 |
| VLD, IPSJ-SLDM | 2007-05-11 10:55 |
Kyoto | Kyodai Kaikan | An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) VLD2007-10 |
Synchronous design methodology is widely used for today's digital circuits. However, highly optimized synchronous design... [more] | VLD2007-10 pp.19-24 |
| VLD, IPSJ-SLDM | 2007-05-11 11:20 |
Kyoto | Kyodai Kaikan | An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-11 |
Originally elliptic curve cryptosystem (ECC) hardware are often required to operate variable key length. Digit-serial mu... [more] | VLD2007-11 pp.25-29 |
| VLD, IPSJ-SLDM | 2007-05-11 11:45 |
Kyoto | Kyodai Kaikan | On power-conscious approach for prefix graph synthesis Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) |
A prefix graph visualizes a global structure of a parallel prefix adder at technology independent level. Several approa... [more] |
VLD2007-12 pp.31-36 |
| VLD, IPSJ-SLDM | 2007-05-11 13:20 |
Kyoto | Kyodai Kaikan | A Flexible Power and Task Modeling for LSI Blocks Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.), Resve Saleh (Univ. of British Columbia) |
Due to the rapid popularization of portable equipments, it becomes very important to make the battery lifetime longer wi... [more] | VLD2007-13 pp.37-42 |
| VLD, IPSJ-SLDM | 2007-05-11 13:45 |
Kyoto | Kyodai Kaikan | A fast maximum delay estimation method for specified yield by statistical static timing analysis. Hiroki Furuya, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) VLD2007-14 |
As VLSI technology advances, the variation of an element delay caused by manufacturing and circuit operation increases.... [more] |
VLD2007-14 pp.43-47 |
| VLD, IPSJ-SLDM | 2007-05-11 14:10 |
Kyoto | Kyodai Kaikan | An algorithm of power grid optimization for high-level floorplan Takayuki Hayashi, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.) |
Recent rapid growth of the narrow and fine patterning technology faces many difficulties of power grid design , e.g. IR ... [more] | VLD2007-15 pp.49-54 |
| VLD, IPSJ-SLDM | 2007-05-11 14:35 |
Kyoto | Kyodai Kaikan | Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) VLD2007-16 |
This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal... [more] |
VLD2007-16 pp.55-59 |
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