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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2007)
Search Results: Keywords 'from:2008-03-05 to:2008-03-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, ICD | 2008-03-05 13:00 |
Okinawa | TiRuRu | Automatic synthesis and verification of practical protocol transducer based on product graph exploration Yuji Ishikawa (Univ. of Tokyo), Satoshi Komatsu, Masahiro Fujita (VDEC, Univ. of Tokyo)  VLD2007-137 ICD2007-160 |
[more] | VLD2007-137 ICD2007-160 pp.1-6 |
| VLD, ICD | 2008-03-05 13:25 |
Okinawa | TiRuRu | Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems Makoto Sugihara (TUT) VLD2007-138 ICD2007-161 |
Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a c... [more] |
VLD2007-138 ICD2007-161 pp.7-12 |
| VLD, ICD | 2008-03-05 13:50 |
Okinawa | TiRuRu | An accurate Algorithm for RTL Power Macro-modeling Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui (Ritsumeikan Univ.) VLD2007-139 ICD2007-162 |
Due to the rapid growth of the electric systems, efficient and lowpower designs have been highly required. To satisfy th... [more] | VLD2007-139 ICD2007-162 pp.13-18 |
| VLD, ICD | 2008-03-05 14:15 |
Okinawa | TiRuRu | Minimizing Minimum Delay Compensations in Datapath Synthesis Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2007-140 ICD2007-163 |
As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI design. The ``setup'' tim... [more] | VLD2007-140 ICD2007-163 pp.19-24 |
| VLD, ICD | 2008-03-05 14:40 |
Okinawa | TiRuRu | An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-141 ICD2007-164 |
[more] | VLD2007-141 ICD2007-164 pp.25-30 |
| VLD, ICD | 2008-03-05 15:20 |
Okinawa | TiRuRu | Analog Floorplan with Soft-Module Configuration Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2007-142 ICD2007-165 |
In MOS analog design, the transistor size is increasing as the supply voltage becomes lower, and the layout configurat... [more] |
VLD2007-142 ICD2007-165 pp.31-36 |
| VLD, ICD | 2008-03-05 15:45 |
Okinawa | TiRuRu | MOS Analog Module Generation Akio Fujii, Takehiko Matsuo, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2007-143 ICD2007-166 |
This paper addresses the module layout configuration issue of MOS analog LSI. We notice that the key characteristic of t... [more] | VLD2007-143 ICD2007-166 pp.37-42 |
| VLD, ICD | 2008-03-05 16:10 |
Okinawa | TiRuRu | [Fellow Memorial Lecture]
Research on VLSI Design and its Future Hiroaki Kunieda (Tokyo Inst. Tech.) |
[more] | |
| VLD, ICD | 2008-03-06 09:15 |
Okinawa | TiRuRu | A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration Tetsuro Ikeda, Atsushi Iwata (Hiroshima Univ.) VLD2007-144 ICD2007-167 |
This paper proposes a high-accuracy and low-power cyclic ADC using digital calibration technique. By using a cascaded... [more] |
VLD2007-144 ICD2007-167 pp.1-6 |
| VLD, ICD | 2008-03-06 09:40 |
Okinawa | TiRuRu | A-90dBm Sensitivity 0.13μm CMOS Bluetooth Transceiver Operating in Wide Temperature Range Kenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shinichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa (Toshiba) VLD2007-145 ICD2007-168 |
A 2.4GHz 0.13um CMOS Bluetooth transceiver achieving the high RX sensitivity and high-quality TX signals between -40C an... [more] | VLD2007-145 ICD2007-168 pp.7-12 |
| VLD, ICD | 2008-03-06 10:05 |
Okinawa | TiRuRu | Design and Analysis of on-chip leakage monitor using MTCMOS Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami (S.I.T.) VLD2007-146 ICD2007-169 |
On cutting-edge semiconductor process, leakage current varies drastically due to process variation and temperature chang... [more] | VLD2007-146 ICD2007-169 pp.13-18 |
| VLD, ICD | 2008-03-06 10:30 |
Okinawa | TiRuRu | Design and Evaluation of the component circuits for the PLL Yuko Kitaji, Masayoshi Tachibana (Kochi Univ. of Tech.) VLD2007-147 ICD2007-170 |
The PLL circuit consists of the phase detector, the loop filter, the voltage-controlled oscillator, and the divider. In ... [more] | VLD2007-147 ICD2007-170 pp.19-24 |
| VLD, ICD | 2008-03-06 11:10 |
Okinawa | TiRuRu | Implementation of LCD Driver by nMOS Dynamic Logic Takuya Hachida, Hideki Matsunaka, Isao Shirakawa (Hyogo Pref. Univ.), Shuji Tsukiyama (Chuo Univ.), Masanori Hashimoto (Osaka Univ.) VLD2007-148 ICD2007-171 |
[more] | VLD2007-148 ICD2007-171 pp.25-30 |
| VLD, ICD | 2008-03-06 11:35 |
Okinawa | TiRuRu | A Study for Implementation of High Speed Circuit Simulator by using FPGA Taiki Hashizume, Seiji Minoura, Tadashi Mizutani, Hironobu Ishijima, Shinichi Nishizawa (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Masahiro Fukui (Ritsumeikan Univ.) VLD2007-149 ICD2007-172 |
With recent advanced technology, simulation plays an important role in the design flow. However, the simulation requires... [more] | VLD2007-149 ICD2007-172 pp.31-36 |
| VLD, ICD | 2008-03-06 12:00 |
Okinawa | TiRuRu | Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders Masayoshi Tachibana (kochi University of Technology) VLD2007-150 ICD2007-173 |
In this paper we address the area, delay and power consumption tradeoff for multiplier with tree-structured partial prod... [more] | VLD2007-150 ICD2007-173 pp.37-42 |
| VLD, ICD | 2008-03-06 13:25 |
Okinawa | TiRuRu | [Invited Talk]
Self descriptive verfication in Continuation based C and it's application to Cell architecture Shinji Kono (University of the Ryukyus) |
[more] | |
| VLD, ICD | 2008-03-06 14:15 |
Okinawa | TiRuRu | Conversion to CbC which used the Cell architecture from C Akira Kamizato, Shinji Kono (Univ of ryukyu) |
We are proposing Continuation based C(CbC), which is a low level language of C. In this paper, the technique which conv... [more] |
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| VLD, ICD | 2008-03-06 14:40 |
Okinawa | TiRuRu | A Case Study on MPEG4 Decoder Design with SystemBuilder Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) VLD2007-151 ICD2007-174 |
This paper presents a case study on designing an MPEG4 decoder system using our system-level design environment named Sy... [more] | VLD2007-151 ICD2007-174 pp.43-48 |
| VLD, ICD | 2008-03-06 15:05 |
Okinawa | TiRuRu | Performance Estimation considering False-paths for System-level Design Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo) VLD2007-152 ICD2007-175 |
In designing today's highly complicated system-LSIs, it is essential to estimate timing information such as worst-case o... [more] | VLD2007-152 ICD2007-175 pp.49-54 |
| VLD, ICD | 2008-03-06 15:45 |
Okinawa | TiRuRu | Superposition Effect Validation of Inductive Coupling Noise Based on Measurement of Interconnect Delay Variation Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2007-153 ICD2007-176 |
Inductive coupling is becoming a design concern for global interconnects in nano-meter technologies. This paper measures... [more] | VLD2007-153 ICD2007-176 pp.55-60 |
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