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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2011)

Search Results: Keywords 'from:2012-01-25 to:2012-01-25'

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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 31  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
10:00
Kanagawa Hiyoshi Campus, Keio University Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications
Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-91 CPSY2011-54 RECONF2011-50
The implementation of TCP/IP is required for various embedded applications to connect into the Internet. However, softwa... [more] VLD2011-91 CPSY2011-54 RECONF2011-50
pp.1-6
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
10:25
Kanagawa Hiyoshi Campus, Keio University Detemination of Vocal Tract Shape on Voice Synthesis Circuit using Shift Register
Keita Manabe, Rika Uegaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-92 CPSY2011-55 RECONF2011-51
Human various voices are made by a shape of phonatory organ that changes its complexity with the muscles.In this paper, ... [more] VLD2011-92 CPSY2011-55 RECONF2011-51
pp.7-12
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
10:50
Kanagawa Hiyoshi Campus, Keio University Sound preprocessing circuit by consonant and vowel recognition system
Keita Okamoto, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-93 CPSY2011-56 RECONF2011-52
The human audition can quickly estimate direction of sound and realize speech recognition under the noisy environment. I... [more] VLD2011-93 CPSY2011-56 RECONF2011-52
pp.13-18
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
11:15
Kanagawa Hiyoshi Campus, Keio University Two Dimensional Array Processor for Moving Object Tracking using Synchronous Data Shift
Takatosi Uchizono, Kazuya Osaku, Akinobu Tsuyuki, Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) VLD2011-94 CPSY2011-57 RECONF2011-53
Moving Object Tracking plays an important role in dynamic image analysis.
The Exclusive Block Matching is one of the ef... [more]
VLD2011-94 CPSY2011-57 RECONF2011-53
pp.19-24
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
11:40
Kanagawa Hiyoshi Campus, Keio University An Image Recognition System with Hierarchical Feature Learning Function
Masahiro Ariizumi, Baku Ogasawara, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-95 CPSY2011-58 RECONF2011-54
In this paper we describe an image recognition system having a hierarchical feature learning function. The feature learn... [more] VLD2011-95 CPSY2011-58 RECONF2011-54
pp.25-30
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
13:30
Kanagawa Hiyoshi Campus, Keio University On a Decomposed MTMDDs for CF Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2011-96 CPSY2011-59 RECONF2011-55
A decomposed multi-terminal multi-valued decision diagrams for characteristic function~(MTMDDs for CF)
represents deco... [more]
VLD2011-96 CPSY2011-59 RECONF2011-55
pp.31-36
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
13:55
Kanagawa Hiyoshi Campus, Keio University An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor
Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ) VLD2011-97 CPSY2011-60 RECONF2011-56
Although the SMT processor which performs two or more threads simultaneously can improve total throughput, the execution... [more] VLD2011-97 CPSY2011-60 RECONF2011-56
pp.37-42
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
14:20
Kanagawa Hiyoshi Campus, Keio University Extension of ITRON Specification OS for Multithreaded Processors
Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) VLD2011-98 CPSY2011-61 RECONF2011-57
Recent advances in embedded systems have demanded high-performance under real-time constraints.Responsive Multithreaded ... [more] VLD2011-98 CPSY2011-61 RECONF2011-57
pp.43-48
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
14:55
Kanagawa Hiyoshi Campus, Keio University Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router
Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.) VLD2011-99 CPSY2011-62 RECONF2011-58
We have proposed a multi-voltage variable-pipeline router in order to reduce power consumption ofNetwork-on-Chip (NoC). ... [more] VLD2011-99 CPSY2011-62 RECONF2011-58
pp.49-54
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
15:20
Kanagawa Hiyoshi Campus, Keio University A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique
Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Takuya Adachi, Hidetoshi Ishijima, Yusuke Kuribara (Univ. of Tsukuba) VLD2011-100 CPSY2011-63 RECONF2011-59
New techniques are strongly desired for signal integrity improvement on PCB traces in GHz-era because conventional imped... [more] VLD2011-100 CPSY2011-63 RECONF2011-59
pp.55-60
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
15:45
Kanagawa Hiyoshi Campus, Keio University A bandwidth control scheme based on a traffic analysis for an on-chip router
Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) VLD2011-101 CPSY2011-64 RECONF2011-60
Recent advances in embedded applications have demanded multi-core processors for embedded systems, and Network-on-Chip (... [more] VLD2011-101 CPSY2011-64 RECONF2011-60
pp.61-66
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
16:20
Kanagawa Hiyoshi Campus, Keio University A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP
Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) VLD2011-102 CPSY2011-65 RECONF2011-61
Recently, the Internet is necessary tool for our daily lives, and the number of the Internet users is increasing particu... [more] VLD2011-102 CPSY2011-65 RECONF2011-61
pp.67-72
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
16:45
Kanagawa Hiyoshi Campus, Keio University Architecture and estimation of reconfigurable processor for multimedia processing
Asuka Hayashi, Shuu'ichirou Yamamoto, Hideo Maejima (Tokyo Tech) VLD2011-103 CPSY2011-66 RECONF2011-62
(To be available after the conference date) [more] VLD2011-103 CPSY2011-66 RECONF2011-62
pp.73-76
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
17:10
Kanagawa Hiyoshi Campus, Keio University Robot Control Unit by Using Dynamically Reconfigurable SU(3) Spin Circuit
Yusaku Yamazaki, Takuya Suzuki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-104 CPSY2011-67 RECONF2011-63
Our laboratory has developed a robot with various sensors, a stereo camera, microphones and a speaker. This robot has be... [more] VLD2011-104 CPSY2011-67 RECONF2011-63
pp.77-82
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
17:35
Kanagawa Hiyoshi Campus, Keio University A Mobile Robot System using Intelligent Circuit in Silicon
Takuya Suzuki, Yusaku Yamazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-105 CPSY2011-68 RECONF2011-64
Intelligent functions required in robots working in human living space, such as actuator control, machine vision, voice ... [more] VLD2011-105 CPSY2011-68 RECONF2011-64
pp.83-88
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
09:00
Kanagawa Hiyoshi Campus, Keio University Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation
Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2011-106 CPSY2011-69 RECONF2011-65
This article presents a method of merging functions during high-level synthesis whose inputs are assembly codes generate... [more] VLD2011-106 CPSY2011-69 RECONF2011-65
pp.89-94
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
09:25
Kanagawa Hiyoshi Campus, Keio University High-Level Synthesis of Hardware Relinkable to Software
Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2011-107 CPSY2011-70 RECONF2011-66
This article presents a method of synthesizing {\em relinkable} hardware for hardware/software codesign utilizing high-l... [more] VLD2011-107 CPSY2011-70 RECONF2011-66
pp.95-100
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
09:50
Kanagawa Hiyoshi Campus, Keio University The Estimation and Experiments of The Hardware Design Method from The UML Modeling Diagrams
Daiki Kano, Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH) VLD2011-108 CPSY2011-71 RECONF2011-67
 [more] VLD2011-108 CPSY2011-71 RECONF2011-67
pp.101-106
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
10:25
Kanagawa Hiyoshi Campus, Keio University Interconnect Reduction in Binding Procedure of HLS
Hao Cong, Song Chen, Takeshi Yoshimura (Waseda Univ.) VLD2011-109 CPSY2011-72 RECONF2011-68
 [more] VLD2011-109 CPSY2011-72 RECONF2011-68
pp.107-109
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
10:50
Kanagawa Hiyoshi Campus, Keio University A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set
Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2011-110 CPSY2011-73 RECONF2011-69
In this paper, a residue-weighted number conversion algorithm using SD(signed-digit) arithmetic for a moduli set \{$2^n$... [more] VLD2011-110 CPSY2011-73 RECONF2011-69
pp.111-116
 Results 1 - 20 of 31  /  [Next]  
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