Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 08:30 |
Kanagawa |
Hiyoshi Campus, Keio University |
Design and implementation of high-level synthesis compiler for stream computation Ryo Ito, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) VLD2013-102 CPSY2013-73 RECONF2013-56 |
High-level synthesis (HLS) has been getting more and more important as FPGAs are more widely used
for various applicati... [more] |
VLD2013-102 CPSY2013-73 RECONF2013-56 pp.1-6 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 08:55 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Unified Software/Reconfigurable Hardware Approach to Solving the Maximum Clique Problem of Large Graphs Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2013-103 CPSY2013-74 RECONF2013-57 |
We propose an algorithm to solve the maximum clique problem of large graphs. The proposed algorithm is a unified softwar... [more] |
VLD2013-103 CPSY2013-74 RECONF2013-57 pp.7-12 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 09:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Takuji Mitsuishi, Hideharu Amano (Keio Univ.) VLD2013-104 CPSY2013-75 RECONF2013-58 |
This paper presents a design of an FPGA-based Blokus Duo solver. It searches a game tree by using
the miniMax algorithm... [more] |
VLD2013-104 CPSY2013-75 RECONF2013-58 pp.13-18 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 09:45 |
Kanagawa |
Hiyoshi Campus, Keio University |
a discussion on hardware architecture of SIFT algorithm for FPGAs utilizing a high-level synthesis tool Naohisa Arakawa, Lin Meng, Tomonori Izumi (Ritsumeikan Univ.) VLD2013-105 CPSY2013-76 RECONF2013-59 |
[more] |
VLD2013-105 CPSY2013-76 RECONF2013-59 pp.19-24 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 10:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Storing and Regenerating Signal Information in a Scalable Hardware System Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60 |
In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating ... [more] |
VLD2013-106 CPSY2013-77 RECONF2013-60 pp.25-30 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 10:50 |
Kanagawa |
Hiyoshi Campus, Keio University |
Hardware Expansion Protocol in a Scalable Hardware System Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) VLD2013-107 CPSY2013-78 RECONF2013-61 |
Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available numb... [more] |
VLD2013-107 CPSY2013-78 RECONF2013-61 pp.31-36 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 11:15 |
Kanagawa |
Hiyoshi Campus, Keio University |
A FPGA/GPU cooperation in nodes communication using PEACH2 Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Tokyo Univ.), Hideharu Amano (Keio Univ.), Taisuke Boku (Univ. of Tsukuba) VLD2013-108 CPSY2013-79 RECONF2013-62 |
PEACH2 (PCI-Express Adaptive Communication Hub 2) is a inter/intra
node communication enhancement system for HA-PACS, w... [more] |
VLD2013-108 CPSY2013-79 RECONF2013-62 pp.37-42 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 11:40 |
Kanagawa |
Hiyoshi Campus, Keio University |
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) VLD2013-109 CPSY2013-80 RECONF2013-63 |
As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been p... [more] |
VLD2013-109 CPSY2013-80 RECONF2013-63 pp.43-48 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 13:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
[Invited Talk]
Research on VLSI Circuits
-- From Solving Problem to Creating Future -- Tadahiro Kuroda (Keio Univ.) VLD2013-110 CPSY2013-81 RECONF2013-64 |
[more] |
VLD2013-110 CPSY2013-81 RECONF2013-64 pp.49-54 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 14:35 |
Kanagawa |
Hiyoshi Campus, Keio University |
The Improvement of Auto-Sharding in MongoDB with Priority-Chunk Yasuhiro Sato, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.) VLD2013-111 CPSY2013-82 RECONF2013-65 |
With the rapid development of the Internet technology,distributed
system is attracted attention.In particular,NoSQL dat... [more] |
VLD2013-111 CPSY2013-82 RECONF2013-65 pp.55-60 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 15:00 |
Kanagawa |
Hiyoshi Campus, Keio University |
Improving the Preformance of Virtual Machine Live Migration by Ordering Memory Page Transfer on Access Pattern Shintaro Nakai, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.) VLD2013-112 CPSY2013-83 RECONF2013-66 |
Unexpected load imbalance at initial placement of virtual machines occur in datacenters providing IaaS Cloud Systems. Th... [more] |
VLD2013-112 CPSY2013-83 RECONF2013-66 pp.61-66 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 15:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Vertical Link On/Off Algorithm for Wireless 3-D NoCs Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) VLD2013-113 CPSY2013-84 RECONF2013-67 |
To reduce power consumption of wireless three-dimension Network-on-Chips (wireless 3-D NoCs), in this paper we propose o... [more] |
VLD2013-113 CPSY2013-84 RECONF2013-67 pp.67-72 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 15:50 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Case for Low-Power Networks using FSO and On/Off Links Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) VLD2013-114 CPSY2013-85 RECONF2013-68 |
Power consumption of interconnection networks incrases as the scale of supercomputers and high-end datacenters increases... [more] |
VLD2013-114 CPSY2013-85 RECONF2013-68 pp.73-78 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 16:30 |
Kanagawa |
Hiyoshi Campus, Keio University |
A 3D FPGA-Array "Vocalise" and its communication system. Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Akihiro Sorimachi, Baku Ogasawara, Masatoshi Sekine (TUAT) VLD2013-115 CPSY2013-86 RECONF2013-69 |
We have developed a 10cm square card with a three-dimensional I/O that installed a 4 million system gate scale FPGA and ... [more] |
VLD2013-115 CPSY2013-86 RECONF2013-69 pp.79-84 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 16:55 |
Kanagawa |
Hiyoshi Campus, Keio University |
An Image Recognition System with Multi-Resolutional Feature Learning on the 3D FPGA-Array "Vocalise" Baku Ogasawara, Satoru Yokota, Jiang Li, Yusuke Atsumari, Hiromasa Kubo, Masatoshi Sekine (TUAT) VLD2013-116 CPSY2013-87 RECONF2013-70 |
We propose and develop "an image recognition system" with multi-resolutional feature learning function. The feature lear... [more] |
VLD2013-116 CPSY2013-87 RECONF2013-70 pp.85-90 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 17:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
Double Caching Memcached Accelerator Eric Shun Fukuda, Tsunaki Sadahisa (Hokkaido Univ.), Hiroaki Inoue, Takashi Takenaka (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) VLD2013-117 CPSY2013-88 RECONF2013-71 |
[more] |
VLD2013-117 CPSY2013-88 RECONF2013-71 pp.91-96 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 17:45 |
Kanagawa |
Hiyoshi Campus, Keio University |
A study on module allocation in multi-FPGA systems Yusuke Hirai, Kazuaki Nakazato (Univ. of the Ryukyus), Mohamed Sofian bin Abu Talip, Mishra Dipikarani, Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. of the Ryukyus) VLD2013-118 CPSY2013-89 RECONF2013-72 |
Computational fluid dynamics (CFD), a powerful tool for aircraft
design and other mechanical designs is a major applica... [more] |
VLD2013-118 CPSY2013-89 RECONF2013-72 pp.97-102 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 08:30 |
Kanagawa |
Hiyoshi Campus, Keio University |
An Experimental Bit-Parallel Solution to Accelerate Smith-Waterman Algorithm Saori Sudo, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) VLD2013-119 CPSY2013-90 RECONF2013-73 |
The Smith-Waterman (SW) algorithm is a computational method to obtain well accorded subsequences between two strings, an... [more] |
VLD2013-119 CPSY2013-90 RECONF2013-73 pp.103-108 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 08:55 |
Kanagawa |
Hiyoshi Campus, Keio University |
Evaluation of parallelization for multiple-precision Cyclic Vector Multiplication Algorithm using CUDA Satoshi Haramura, Hiroto Kagotani, Yasuyuki Nogami, Yuji Sugiyama (Okayama Univ.) VLD2013-120 CPSY2013-91 RECONF2013-74 |
[more] |
VLD2013-120 CPSY2013-91 RECONF2013-74 pp.109-112 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 09:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
Performance Evaluation of Graph Database using Multicore and GPU Shin Morishima, Hiroki Matsutani (Keio Univ.) VLD2013-121 CPSY2013-92 RECONF2013-75 |
Graph databases use graph structures to store data sets as nodes, edges, and properties. They are used to store and sear... [more] |
VLD2013-121 CPSY2013-92 RECONF2013-75 pp.113-118 |