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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) (Searched in: 2022)
Search Results: Keywords 'from:2023-01-23 to:2023-01-23'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)  VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] | VLD2022-56 RECONF2022-79 pp.1-6 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] | VLD2022-57 RECONF2022-80 pp.7-12 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU) VLD2022-58 RECONF2022-81 |
The SA method is widely used as a logic device placement method for FPGAs. We have introduced neural networks to the pla... [more] | VLD2022-58 RECONF2022-81 pp.13-18 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 11:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Evaluation of reduced routing resources for HPC-Oriented CGRAs Carlos Cortes, Boma Adhi, Tomohiro Ueno (RIKEN Center for Computational Science (R-CCS)), Yiyu Tan (Dept of Systems Innovation Engineering Iwate Univ.), Takuya Kojima (Information Science and Technology The Univ. of Tokyo), Artur Podobas (KTH Royal Inst. of Technology), Kentaro Sato (RIKEN Center for Computational Science (R-CCS)) VLD2022-59 RECONF2022-82 |
[more] | VLD2022-59 RECONF2022-82 pp.19-23 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
[Invited Talk]
Can we say "No FPGA, No Smart City"?
-- Let's declare if we do a smart city, we need FPGAs. -- Hiroaki Nishi (Keio Univ.) VLD2022-60 RECONF2022-83 |
From the perspective of a chair of standardization of technologies related to Smart City information infrastructure, we ... [more] | VLD2022-60 RECONF2022-83 p.24 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 16:10 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
VLD2022-61 RECONF2022-84 |
(To be available after the conference date) [more] | VLD2022-61 RECONF2022-84 pp.25-26 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 16:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Interface development for Python use of FPGA cluster ESSPER Taiki Watanabe (TUT), Kentaro Sano (R-CCS), Yukinori Sato (TUT) VLD2022-62 RECONF2022-85 |
[more] | VLD2022-62 RECONF2022-85 pp.27-28 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 16:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
A study on optimisation of Back Projection Processing of CT Images using FPGA Jumpei Mano, Takaaki Miyajima (Meiji Univ), Peng Chen (AIST), Mohamed Wahib, Kentaro Sano (RIKEN) VLD2022-63 RECONF2022-86 |
[more] | VLD2022-63 RECONF2022-86 pp.29-30 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 16:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
VLD2022-64 RECONF2022-87 |
[more] | VLD2022-64 RECONF2022-87 pp.31-33 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM Motoki Kamibayashi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Masanori Hashimoto (Kyoto Univ.) VLD2022-65 RECONF2022-88 |
In recent years, as the memory capacity of computer systems has increased,the reliability of the system has decreased.So... [more] | VLD2022-65 RECONF2022-88 pp.34-39 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Study on Wireless Transmission Data Reduction Method and Its Implementation in Emotion Recognition System Using Electroencephalogram Yuuki Harada, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.) VLD2022-66 RECONF2022-89 |
Recently, there has been a great deal of research on emotion recognition and its application using electroencephalogram.... [more] | VLD2022-66 RECONF2022-89 pp.40-44 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips Chiharu Shiro (Ritsumeiakn Univ.), Hiroki Nishikawa (Osaka Univ.), Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeiakn Univ.) VLD2022-67 RECONF2022-90 |
Digital microfluidic biochips (DMFB) have attracted attention in the biochemical and medical industries. A micro electro... [more] | VLD2022-67 RECONF2022-90 pp.45-49 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 11:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2022-68 RECONF2022-91 |
Binarized neural networks (BNN) allow compact hardware implementation by binarizing weight values and neuron activations... [more] | VLD2022-68 RECONF2022-91 pp.50-55 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Implementing a quantum computer simulator Qulacs on FPGAs Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba) VLD2022-72 RECONF2022-95 |
Quantum computer simulation is indispensable for quantum algorithm research since the results of real quantum computers... [more] |
VLD2022-72 RECONF2022-95 pp.74-79 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 13:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
An Implementation of Generic IP-cores for Linux by Using VIRTIO Interface Kota Asanuma (TUAT/e-trees), Takefumi Miyoshi (e-trees) VLD2022-70 RECONF2022-93 |
[more] | VLD2022-70 RECONF2022-93 pp.62-67 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 14:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Leveraging dynamic parameter for solution search acceleration in bio-inspired hardware SAT solver Anh Hoang Ngoc Nguyen (Fujitsu ltd.) VLD2022-71 RECONF2022-94 |
For decision making, various systems need to solve combinatorial optimization problems, which are often encoded as a Sat... [more] | VLD2022-71 RECONF2022-94 pp.68-73 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 14:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Akinobu Tomori (Univ. Ryukyu), Yasunori Osana (Univ. Ryukyus) VLD2022-69 RECONF2022-92 |
[more] | VLD2022-69 RECONF2022-92 pp.56-61 |
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