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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Hirofumi Hamamura
Vice Chair Nagisa Ishiura
Secretary Toshiyuki Shibuya, Hiroyuki Ochi

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Takanobu Baba
Vice Chair Nobuki Kajihara, Toshinori Sueyoshi
Secretary Hiroko Midorikawa, Akira Asato
Assistant Takashi Yokota

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Toshinori Sueyoshi
Vice Chair Akira Nagoya, Tomomi Sato
Secretary Tetsuo Hironaka, Yuichiro Shibata
Assistant Masahiro Iida

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]

Conference Date Wed, Jan 17, 2007 13:15 - 17:40
Thu, Jan 18, 2007 09:45 - 16:10
Topics FPGA and its Application, etc. 
Conference Place Hiyoshi Campus, Keio University 
Transportation Guide 2-minute walk from Hiyoshi Station (Tokyu-Toyoko Line)
http://www.keio.ac.jp/access2.html#hiyosi
Contact
Person
Prof. Hideharu Amano
045-560-1063

Wed, Jan 17 PM 
Chair: Hideharu Amano (Keio Univ.)
13:15 - 14:30
(1) 13:15-13:40 Achieve a preprocessing part of auditory sense with circuit Yuya Usami, Hidehiko Arai, Etu Sou, Kazushi Takahashi, Toshitaka Nagano, Masatoshi Sekine (TUAT)
(2) 13:40-14:05 FGPA Implementation of the Computing System RAPLAS for Ray-Tracing Daichi Zaitsu, Yoshiyuki Kaeriyama, Kenichi Suzuki, Ryusuke Egawa (Tohoku Univ.), Nobuyuki Ohba (IBM Japan, Ltd.), Tadao Nakamura (Tohoku Univ.)
(3) 14:05-14:30 Face detection with the union of hardware and software Masatoshi Yokokawa, Ichiro Sudo, Tomomi Yuno, Masatoshi Sekine (TUAT)
  14:30-14:50 Break ( 20 min. )
Wed, Jan 17 PM 
Chair: Kiyoharu Hamaguchi (Osaka Univ.)
14:50 - 15:40
(4) 14:50-15:15 Design of Residue Dividers Using Signed-Digit Number Residue Addition Peng Jia, Shugang Wei (Gunma Univ.)
(5) 15:15-15:40 GF(2^m) Digit-Serial Multiplier for Elliptic Curve Cryptosystem Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Masao Yanagisawa, Satoshi Goto, Tatsuo Ohtsuki (Waseda Univ)
  15:40-16:00 Break ( 20 min. )
Wed, Jan 17 PM 
Chair: Nobuki Kajihara (NEC)
16:00 - 17:40
(6) 16:00-16:25 A Parallel Algorithm Based on Genetic Algorithm and Tabu Search for LSI Floorplanning and Its Implementation on a PC Cluster Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
(7) 16:25-16:50 A Hardware Algorithm for the Quadratic Assignment Problem Based on Tabu Search Using FPGAs Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
(8) 16:50-17:15 Converting PLC instruction sequence into logic circuit: implementation and evaluation Masanori Akinaka, Shuichi Ichikawa (Toyohashi Univ. Tech.)
(9) 17:15-17:40 On efficient cut enumeration in technology mapping for FPGA Yusuke Matsunaga (Kyushu Univ.)
  - Banquet(18:00--20:00)
Thu, Jan 18 AM 
Chair: Yusuke Matsunaga (Kyushu Univ.)
09:45 - 11:50
(10) 09:45-10:10 Optimum Code Scheduling for Clustered VLIW DSP Using Pseudo Boolean Satisfiability Ryo Kobayashi, Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.)
(11) 10:10-10:35 Test Suite for C Compilers and Its Generating Tool testgen Yuki Uchiyama (Kwansei Gakuin Univ.), Nobuyuki Hikichi (SRA), Nagisa Ishiura, Yuji Nagamatsu (Kwansei Gakuin Univ.)
(12) 10:35-11:00 Development of C-Compiler for Educational Microprocessor COMET II Ken Matsuda, Akira Sato, Kensuke Mori, Toshiyuki Tsutsumi (Meiji Univ.)
(13) 11:00-11:25 CoDaMa: An XML-based Framework for Manipulating CDFGs Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(14) 11:25-11:50 Model Checking of Cycle Accurate Hardware Behavior Models with Instantaneous Communication Hirohisa Fujita, Masahiko Hamada, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.)
  11:50-13:00 Lunch Break ( 70 min. )
Thu, Jan 18 PM 
Chair: Akira Nagoya (Okayama Univ.)
13:00 - 14:40
(15) 13:00-13:25 Construction Method for a Circuit by Multiplication Satoshi Yano, Hayato Higuchi, Taichi Nagamoto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
(16) 13:25-13:50 Analysis of design architecture of ePLX ( embedded Programmable Logic matriX) and Evaluation of circuit mapping Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.)
(17) 13:50-14:15 Implementation of Dynamically Reconfigurable Processor MuCCRA Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Hiroki Matsutani, Vasutan Tunbunheng, Adepu Parimala, Takashi Nishimura, Masaru Kato, Shotaro Saito, Toru Sano, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano (Keio Univ.)
(18) 14:15-14:40 A Scheduling Algorithm for Multicast Configuration Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Hiroki Matsutani, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Toru Sano, Masaru Kato, Shotaro Saito, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano (Keio Univ.)
  14:40-14:55 Break ( 15 min. )
Thu, Jan 18 PM 
Chair: Yuichiro Shibata (Nagasaki Univ.)
14:55 - 16:10
(19) 14:55-15:20 Adoption and Evaluation of FPGA Partial Reconfiguration for a Run-time Reconfigurable System Yukinobu Kiyota, Taiichiro Yatsunami, Takeru Kisanuki, Hideaki Yoshihiro, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(20) 15:20-15:45 Design and Implementation of Self Run-time Partial Reconfiguration System Yohei Hori (AIST), Hiroyuki Yokoyama (KDDI Labs.), Hirofumi Sakane, Kenji Toda (AIST)
(21) 15:45-16:10 A Study of Efficient Context Switching Methods on Dynamically Reconfigurable Hardware Masaharu Yoneda, Masaru Fukushi, Susumu Horiguchi (Tohoku Univ.)

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Shibuya Toshiyuki(Fujitsu Laboratories)
E--mail:bu
Tel.044-754-2663 
Announcement You will see the latest information at the below WEB page.
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Takashi Yokota (Utsunomiya Univ.)
TEL +81-28-689-6290, FAX +81-28-689-6290
E--mail: isu-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Masahiro IIDA (Kumamoto Univ.)
E--mail: ii-u
TEL: +81-96-342-3649 FAX: +81-96-342-3649 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  


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