IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev DC Conf / Next DC Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Hiroshi Takahashi (Ehime Univ.)
Vice Chair Tatsuhiro Tsuchiya (Osaka Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Conference Date Tue, Mar 1, 2022 09:30 - 17:00
Conference Place  
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on DC.

Tue, Mar 1 AM 
09:30 - 10:45
(1) 09:30-09:55 Design of Successive Approximation ADC using Standard Cell Design Flow DC2021-64 Hiroshi Hirano, Satoshi Komatsu (Tokyo Denki Univ.)
(2) 09:55-10:20 Multi-process Automatic Generation System for ADC Using Standard cell DC2021-65 Takumi Fukushima, Satoshi Komatsu (Tokyo Denki Univ.)
(3) 10:20-10:45 DC2021-66
  10:45-10:55 Break ( 10 min. )
Tue, Mar 1 AM 
10:55 - 11:45
(4) 10:55-11:20 On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement DC2021-67 Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT)
(5) 11:20-11:45 Applicability Evaluation of the Delay Testable Circuit to PUF DC2021-68 Eisuke Ohama, Haruka Chino, Hiroyuki Yotuyanagi, Masaki Hashizume (Tokushima Univ.)
  11:45-12:55 Break ( 70 min. )
Tue, Mar 1 PM 
12:55 - 14:10
(6) 12:55-13:20 A TMR-Based Approximate Corrector for Fail-Operational Systems DC2021-70 Mitsuyoshi Ashida, Tomoo Inoue, Hideyuki Ichihara (City Univ)
(7) 13:20-13:45 Delay Fault Test Pattern Generation of Fault Tolerant Design Using Approximate Computing DC2021-71 Koji Makino, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
(8) 13:45-14:10 A Logic Locking Method based on SFLL-hd at Register Transfer Level DC2021-72 Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.)
  14:10-14:20 Break ( 10 min. )
Tue, Mar 1 PM 
14:20 - 15:35
(9) 14:20-14:45 Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability DC2021-73 Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech)
(10) 14:45-15:10 SAT-based LFSR Seed Generation for Delay Fault BIST DC2021-74 Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.)
(11) 15:10-15:35 State assignment method to improve transition fault coverage for controllers including invalid states DC2021-75 Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
  15:35-15:45 Break ( 10 min. )
Tue, Mar 1 PM 
15:45 - 17:00
(12) 15:45-16:10 Evaluation of Don't Care Filling Method of Control Signals to Enhance Fault Diagnosability for Logic and Timing Fault DC2021-76 Kohei Tsuchibuchi, Xu Haofeng, Yuya Chida, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ)
(13) 16:10-16:35 An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information DC2021-77 Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.)
(14) 16:35-17:00 DC2021-78

Other published manuscript(s)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E--mail: ain-u 

Last modified: 2022-02-15 14:38:58

Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
[Cover and Index of IEICE Technical Report by Issue]

[Presentation and Participation FAQ] (in Japanese)

[Return to DC Schedule Page]   /  
 Go Top  Go Back   Prev DC Conf / Next DC Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan