Thu, Apr 12 AM  09:00 - 10:30
(1)	09:00-09:30	MRAM Cell Technology for High-speed SoCs ICD2007-1	Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Kenichi Shimura, Naoki Kasai (NEC)
(2)	09:30-10:00	Design of Low Read Bias Voltage and High Speed Sense Amplifier for STT-MRAM ICD2007-2	Yoshihiro Ueda, Yoshihisa Iwata, Tsuneo Inaba, Yuui Shimizu, Kiyotaro Itagaki, Kenji Tsuchida (Toshiba)
(3)	10:00-10:30	A high-density 1T-4MTJ MRAM with Self-Reference Sensing Scheme ICD2007-3	Yasumitsu Murai, Hiroaki Tanizaki (Renesas Design), Takaharu Tsuji, Jun Otani, Yuichiro Yamaguchi, Haruo Furuta, Shuichi Ueno, Tsukasa Oishi, Masanori Hayashikoshi, Hideto Hidaka (Renesas)
Thu, Apr 12 AM  10:40 - 12:00
(4)	10:40-11:10	Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor ICD2007-4	Takaho Tanigawa, Yasushi Yamagata, Hiroki Shirai, Hirotoshi Sugimura, Tomoko Wake, Ken Inoue, Takashi Sakoh, Masato Sakao (NECEL)
(5)	11:10-12:00	[Invited Talk] A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current ICD2007-5	Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi)
Thu, Apr 12 PM  13:00 - 15:20
(6)	13:00-13:50	[Invited Talk] 2-Mb SPRAM (SPin-transfer torque RAM) with Bit-by-bit Bi-Directional Current Write and Parallelizing-Direction Current Read ICD2007-6	Riichiro Takemura, Takayuki Kawahara, Katsuya Miura (Hitachi), Jun Hayakawa (Hitachi/Tohoku Univ.), Shoji Ikeda, Young Min LEE, Ryutaro Sasaki (Tohoku Univ.), Yasushi Goto, Kenchi Ito (Hitachi), Toshiyasu Meguro, Fumihiro Matsukura (Tohoku Univ.), Hiromasa Takahashi (Hitachi/Tohoku Univ.), Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.)
(7)	13:50-14:20	A Novel Two-Port SRAM for Low Bitline Power Using Majority Logic and Data-Bit Reordering ICD2007-7	Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
(8)	14:20-14:50	A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform ICD2007-8	Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)
(9)	14:50-15:20	High-speed Operation SRAM cell using Bulk-type Thyristor ICD2007-9	Taro Sugizaki, Motoaki Nakamura, Masashi Yanagita, Motonari Honda, Mitsuko Shinohara, Tetsuya Ikuta, Tomokazu Ohchi, Katsuhisa Kugimiya, Ryo Yamamoto, Saori Kanda, Ikuhiro Yamamura, Kojiro Yagami, Tatsuji Oda (Sony corp.)
Thu, Apr 12 PM  15:30 - 17:30
(10)	15:30-17:30	[Panel Discussion] *	Masahiko Yoshimoto (Kobe Univ.)
Fri, Apr 13 AM  09:10 - 10:30
(11)	09:10-09:40	Floating Body RAM Technology and its Scalability to 32nm Node ICD2007-10	Hiroomi Nakajima, Naoki Kusunoki, Tomoaki Shino (Toshiba), Tomoki Higashi (TOSMEC), Takashi Ohsawa, Katsuyuki Fujita, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Ryo Fukuda, Yohji Watanabe, Yoshihiro Minami (Toshiba), Atsushi Sakamoto (TJ), Jun Nishimura, Takeshi Hamamoto, Akihiro Nitayama (Toshiba)
(12)	09:40-10:30	[Invited Talk] A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die ICD2007-11	Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology)
Fri, Apr 13 AM  10:30 - 11:50
(13)	10:30-11:00	A 0.14pJ/b Inductive-Coupling Transceiver ICD2007-12	Noriyuki Miura, Hiroki Ishikuro (Keio Univ.), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.)
(14)	11:00-11:50	[Invited Talk] A high density embedded memory for Soc: Twin transistor RAM(TT-RAM) ICD2007-13	Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka (Renesas)
Fri, Apr 13 PM  13:00 - 14:50
(15)	13:00-13:50	[Invited Talk] High Speed Unipolar Switching Resistance RAM (RRAM) Technology ICD2007-14	Yasunari Hosoi, Yukio Tamai, T. Ohnishi, K. Ishihara, T. Shibuya, Y. Inoue, S. Yamazaki, T.Nakano, Shigeo Ohnishi, Nobuyoshi Awaya (Sharp), I. H. Inoue, Hisashi Shima (AIST(NEDO)), Hiroyuki Akinaga, Hidenori Takagi, Hiroshi Akoh (AIST(CERC))
(16)	13:50-14:20	Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention ICD2007-15	Hiroshi Sunamura, Taeko Ikarashi, Ayuka Morioka, Setsu Kotsuji, Makiko Oshida, Nobuyuki Ikarashi, Shinji Fujieda, Hirohito Watanabe (NEC)
(17)	14:20-14:50	25nm SONOS-type Memory Device usinh Double Tunnel Junction ICD2007-16	Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba Co.)

Contact Address and Latest Schedule Information
ICD	Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
	Contact Address	Yoshiharu Aimoto (NEC Electronics Corporation) TEL +81-44-435-1258, +81-44-435-1878 E-:aicel

Last modified: 2007-03-30 14:57:54