Tue, May 13 AM  09:00 - 11:00
(1)	09:00-09:30	Branch Target Predictor Utilizing Context Base Value Predictor	Tetsurou Hirashima (NRI), Hajime Shimada (Kyoto Univ.), Shinobu Miwa (TUAT), Shinji Tomita (Kyoto Univ.)
(2)	09:30-10:00	Speculation scheme that continues executing mispredicted instructions	Takanobu Kita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo)
(3)	10:00-10:30	Evaluation of Area-Oriented Register Cache	Ryota Shioya (Univ. Tokyo), Hidetsugu Irie (JST), Masahiro Goshima, Shuichi Sakai (Univ. Tokyo)
(4)	10:30-11:00	An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping	Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.)
	11:00-11:15	Break ( 15 min. )
Tue, May 13   11:15 - 12:15
(5)	11:15-12:15	[Invited Talk] Multi - Core Processor for Computer System ICD2008-21	Yoshio Miki (HITACHI)
	12:15-13:45	Lunch Break ( 90 min. )
Tue, May 13   13:45 - 18:00
(6)	13:45-14:45	[Invited Talk] Cell Broadband Engine and SpursEngine as a Muti-core Processor ICD2008-22	Hiroo Hayashi (Toshiba Corp.)
(7)	14:45-15:45	[Invited Talk] Intel's vision -- The Demand for Many Cores: Tera-Scale Usage Models -- ICD2008-23	Yoshie Munakata (Intel)
	15:45-16:00	Break ( 15 min. )
(8)	16:00-18:00	[Panel Discussion] What We Have To Do in Multi-Core Era?	Shinji Tomita (Kyoto Univ.), Naoki Nishi (NEC), Mitsuo Saito (Toshiba), Yoshie Munakata (Intel), Aiichiro Inoue (Fujitsu), Toshiyuki Sanuki (IBM Japan), Yasushi Fukunaga (Hitachi)
Wed, May 14 AM  09:00 - 11:00
(9)	09:00-09:30	A Scalable Multi-core Processor for Mobile Multimedia Applications ICD2008-25	Hiroyuki Usui, Shuou Nomura, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Jun Tanabe, Masato Uchiyama, Takashi Miyamori, Yoshiro Tsuboi (Toshiba)
(10)	09:30-10:00	Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors ICD2008-26	Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas)
(11)	10:00-10:30	Multicore Debug Function for Embedded Processor	Jun Sakiyama, Makoto Saen (Hitachi, Ltd.), Takehiro Shimizu (Renesas Technology Corp.)
(12)	10:30-11:00	PSI-SIM: Performance Prediction for Peta-Scale Supercomputers with Thousands of Multi-core Processors	Koji Inoue (Kyushu Univ.), Ryutaro Susukita (IST), Hisashige Ando, Shigeru Ishizuki, Hidemi Komatsu (Fujitsu), Yuichi Inadomi, Hiroaki Honda (Kyushu Univ.), Shuji Yamamura (Fujitsu), Hidetomo Shibamura (ISIT), Yunqing Yu, Mutsumi Aoyagi (Kyushu Univ.), Yasunori Kimura (Fujitsu), Kazuaki Murakami (Kyushu Univ.)
	11:00-11:15	Break ( 15 min. )
Wed, May 14 AM  11:15 - 12:15
(13)	11:15-11:45	Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates ICD2008-28	Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
(14)	11:45-12:15	Architecture of a Stereo Matching VLSI Based on Recursive Computation ICD2008-29	Keita Tanji, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
	12:15-13:45	Lunch Break ( 90 min. )
Wed, May 14 PM  13:45 - 15:15
(15)	13:45-14:15	Automatic Parallelization of Restricted C Programs using Pointer Analysis	Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
(16)	14:15-14:45	Performance Balancing: An Efficient Helper-Thread Execution on CMPs	Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
(17)	14:45-15:15	Adaptive Management of Parallelism on Transactional Memories	Susumu Takeda, Keita Shimasaki, Koji Inoue, Kazuaki Murakami (kyushu Univ.)
	15:15-15:30	Break ( 15 min. )
Wed, May 14 PM  15:30 - 16:30
(18)	15:30-16:00	A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor	Yu Kojima, Daisuke Ikebuchi, Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.), Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami (Shibaura Inst of Tech), Tetsuya Sunada, Jun Kanai, Mitaro Namiki (Tokyo Univ. of Agri & Tech), Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo)
(19)	16:00-16:30	Considering Performance and Area Overhead in DVS System Utilizing Input Variations	Yuji Kunitake (Kyushu U.), Toshinori Sato (Fukuoka U.), Hiroto Yasuura (Kyushu U.)
Wed, May 14 PM  16:30 - 18:00
(20)	16:30-17:00	A Low-Latency On-Chip Router Architecture with Prediction Mechanism	Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.), Tsutomu Yoshinaga (UEC)
(21)	17:00-17:30	Performance Balancing: An Implementation of Efficient On-chip Memory Hierarchy on Cell/B.E.	Tetsuo Hayashi, Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
(22)	17:30-18:00	Quantitative Analysis of Memory Workload on Chip-Multiprocessors	Mitsuaki Yamaguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)

Contact Address and Latest Schedule Information
ICD	Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
	Contact Address	Yoshio Hirose (Fujitsu Laboratories Ltd.) TEL +81-44-754-2783, +81-44-754-2744 E-:y
IPSJ-ARC	Special Interest Group on Computer Architecture (IPSJ-ARC)   [Latest Schedule]
	Contact Address	Koji Inoue（Kyushu University） TEL 092-802-3793, FAX 092-802-3786 E-:inoue"at"i.kyushu-u.ac.jp

Last modified: 2008-05-07 09:52:53