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Technical Committee on Hardware Security (HWS) [schedule] [select]
Chair Makoto Nagata (Kobe Univ.)
Vice Chair Yuichi Hayashi (NAIST), Daisuke Suzuki (Mitsubishi Electric)
Secretary Hirotake Yamamotoi (Sony Semiconductor Solutions), Daisuke Fujimotoi (NAIST)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Minako Ikeda (NTT)
Vice Chair Shigetoshi Nakatake (Univ. of Kitakyushu)
Secretary Makoto Miyamura (NBS), Masashi Imai (Hirosaki Univ.)
Assistant Takuma Nishimoto (Hitachi)

Conference Date Wed, Mar 1, 2023 11:00 - 17:40
Thu, Mar 2, 2023 09:30 - 17:40
Fri, Mar 3, 2023 09:30 - 17:40
Sat, Mar 4, 2023 10:00 - 14:45
Address 2-15-23 Kume, Naha City, Okinawa
Transportation Guide
Sponsors This conference is co-sponsored by IEEE SSCS Japan Chapter and IEEE SSCS Kansai Chapter.
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on HWS, VLD.

Wed, Mar 1 AM  VLD
11:00 - 13:25
(1) 11:00-11:25 Measured Evaluation of BTI Degradation in a 65nm FDSOI Process using Ring Oscillators with Same Circuit Structure VLD2022-73 HWS2022-44 Daisuke Kikuta (KIT), Ryo Kishida (TPU), Kazutoshi Kobayashi (KIT)
(2) 11:25-11:50 Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test VLD2022-74 HWS2022-45 Daisuke Goeda (KIT), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michihiro Shintani (KIT)
(3) 11:50-12:15 Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process VLD2022-75 HWS2022-46 Yuta Shintani, Michiko Inoue (Naist), Michihiro Shintani (Kyoto Institute of Technology)
  12:15-13:25 Break ( 70 min. )
Wed, Mar 1 PM  VLD
13:25 - 14:55
(4) 13:25-13:50 Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices VLD2022-76 HWS2022-47 Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT)
(5) 13:50-14:15 Circuit Optimization and Simulation Evaluation for Ultra-Low Voltage of LRPUF Using Manufacturing Variability of Leakage Current VLD2022-77 HWS2022-48 Shunkichi Hata, Kimiyoshi Usami (SIT)
(6) 14:15-14:40 A Study on Interface Circuits for Burst Transfers from Synchronous to Asynchronous Circuits VLD2022-78 HWS2022-49 Shogo Semba, Hiroshi Saito (UoA)
  14:40-14:55 Break ( 15 min. )
Wed, Mar 1 PM  VLD
14:55 - 16:25
(7) 14:55-15:20 High fidelity mask pattern generation method by amplitude component evaluation VLD2022-79 HWS2022-50 Yu Horimoto, Sota Saito, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA)
(8) 15:20-15:45 A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation VLD2022-80 HWS2022-51 Sota Saito, Yu Horimoto, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA)
(9) 15:45-16:10 A Feature Vector Considering Characteristics of Optical System for Lithography Hotspot Detection VLD2022-81 HWS2022-52 Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama (HCU)
  16:10-16:25 Break ( 15 min. )
Wed, Mar 1 PM  VLD
16:25 - 17:40
(10) 16:25-16:50 Large-scale SAT Solution Search by FPGA Implementation of Attraction-Repulsion Control-Type Amoeba Algorithm VLD2022-82 HWS2022-53 Torao Okuyama (Keio Univ.), Masashi Aono, Kaori Okoda (Amoeba Energy), Hideharu Amano (Keio Univ.)
(11) 16:50-17:15 A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs VLD2022-83 HWS2022-54 Tomohisa Kawakami, Chiharu Shiro (Ritsumeikan Univ.), Hiroki Nishikawa (Osaka Univ.), Kong Xiangbo, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ.)
(12) 17:15-17:40 Routing with cleaning in MEDA biochips VLD2022-84 HWS2022-55 Shiro Chiharu (Ritsumei), Nishikawa hiroki (Osaka), Xiangbo Kong, Tomiyama Hiroyuki, Yamashita Shigeru (Ritsumei)
Thu, Mar 2 AM  VLD
09:30 - 11:00
(13) 09:30-09:55 VLD2022-85 HWS2022-56
(14) 09:55-10:20 Implementation of power-outage tolerant VLSI system using asynchronous circuits VLD2022-86 HWS2022-57 Masashi Imai (Hirosaki Univ.)
(15) 10:20-10:45 A Study and an Evaluation of the High Performance Deep Neural Network Inference circuit on FPGAs VLD2022-87 HWS2022-58 Ryo Yamamoto, Kenya Sugihara, Yoshihiro Ogawa (Mitsubishi Electric)
  10:45-11:00 Break ( 15 min. )
Thu, Mar 2 AM  VLD
11:00 - 13:25
(16) 11:00-11:25 VLD2022-88 HWS2022-59
(17) 11:25-11:50 Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution VLD2022-89 HWS2022-60 Mineo Kaneko (JAIST)
(18) 11:50-12:15 Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis VLD2022-90 HWS2022-61 Masayuki Usui, Shinya Takamaeda (UTokyo)
  12:15-13:25 Break ( 70 min. )
Thu, Mar 2 PM  VLD
13:25 - 15:20
(19) 13:25-13:50 [Memorial Lecture]
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects VLD2022-91 HWS2022-62
Takuma Nagao (NAIST), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (Sony Semiconductor Manufacturing), Michiko Inoue (NAIST), Michihiro Shintani (Kyoto Institute of Technology)
(20) 13:50-14:15 [Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology VLD2022-92 HWS2022-63
Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC)
(21) 14:15-14:40 [Memorial Lecture]
DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits [Memorial lecture] VLD2022-93 HWS2022-64
Dehua Liang (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.), Noriyuki Miura, Jun Shiomi (Osaka Univ.)
(22) 14:40-15:05 [Memorial Lecture]
An SMT-Solver-based Synthesis of NNA-Compliant antum Circuits Consisting of CNOT, H and T Gates VLD2022-94 HWS2022-65
Kyehei Seino, Shigeru Yamashita (Ritsumeikan University)
  15:05-15:20 Break ( 15 min. )
Thu, Mar 2 PM  HWS
15:20 - 16:25
(23) 15:20-15:45 Secure Cache System against On-Chip Threats VLD2022-95 HWS2022-66 Keisuke Kamahori, Shinya Takamaeda (UTokyo)
(24) 15:45-16:10 Hiding Memory Structures for IP Protection VLD2022-96 HWS2022-67 Sun Tanaka, Shinya Takamaeda (UTokyo)
  16:10-16:25 Break ( 15 min. )
Thu, Mar 2 PM  VLD
16:25 - 17:40
(25) 16:25-16:50 Multiple Constant Convolution with Minimum Number of Full Adders. VLD2022-97 HWS2022-68 Kota Kuga, Shinya Takamaeda (UTokyo)
(26) 16:50-17:15 Reducing Conflict Misses with Multiple Indexings in Compressed Caches VLD2022-98 HWS2022-69 Tasuku Fukami, Shinya Takamaeda (UTokyo)
(27) 17:15-17:40 Communication-Efficient Federated Learning with Gradient Boosting Decision Trees VLD2022-99 HWS2022-70 Kotaro Shimamura, Shinya Takamaeda (UTokyo)
Fri, Mar 3 AM  VLD
09:30 - 10:45
(28) 09:30-09:55 Global routing method imitating car path search VLD2022-100 HWS2022-71 Yusuke Yamaguchi, Kunihiro Fujiyoshi (TUAT)
(29) 09:55-10:20 Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing VLD2022-101 HWS2022-72 Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat)
(30) 10:20-10:45 Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints VLD2022-102 HWS2022-73 Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (JEDAT)
  10:45-11:00 Break ( 15 min. )
Fri, Mar 3 AM  VLD
11:00 - 12:15
(31) 11:00-11:25 VLD2022-103 HWS2022-74 Yusei Yano, Shinji Nozaki, Tomohide Aizawa, Yukihide Kohira (Univ. of Aizu)
(32) 11:25-11:50 Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits VLD2022-104 HWS2022-75 Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.)
(33) 11:50-12:15 A Seed Selection Method for Minimizing Test Execution Time in Logic BIST Using Pseudo-Boolean Optimization VLD2022-105 HWS2022-76 Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)
  12:15-13:25 Break ( 70 min. )
Fri, Mar 3 PM  VLD
13:25 - 15:20
(34) 13:25-13:50 High-Performance and Programmer-Friendly Secure Non-Volatile Memory using Temporal Memory-Access Redirection VLD2022-106 HWS2022-77 Ryo Koike, Shinya Takamaeda (UTokyo)
(35) 13:50-14:15 A Logic Locking Method based on Function Modification Circuit VLD2022-107 HWS2022-78 Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.)
(36) 14:15-14:40 N/A VLD2022-108 HWS2022-79 Yuka Ikegami, Kazuki Yamashita (Waseda Univ.), Kento Hasegawa, Kazuhide Fukushima, Shinsaku Kiyomoto (KDDI Research, Inc.), Nozomu Togawa (Waseda Univ.)
(37) 14:40-15:05 Toggle-based simulation of side-channel attack against multiplier for pairing-based cryptography VLD2022-109 HWS2022-80 Saito Kikuoka, Makoto Ikeda (Tokyo Univ.)
  15:05-15:20 Break ( 15 min. )
Fri, Mar 3 PM  HWS
15:20 - 16:25
(38) 15:20-15:45 Design optimization of TFHE-based 4+ input homomorphic logic gates by error controlling VLD2022-110 HWS2022-81 Yinfan Zhao, Makoto Ikeda (Tokyo Univ.)
(39) 15:45-16:10 Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA VLD2022-111 HWS2022-82 Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)
  16:10-16:25 Break ( 15 min. )
Fri, Mar 3 PM  VLD
16:25 - 17:40
(40) 16:25-16:50 NA VLD2022-112 HWS2022-83 Ryusei Eda, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
(41) 16:50-17:15 NA VLD2022-113 HWS2022-84 Hibiki Nakanishi, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
(42) 17:15-17:40 NA VLD2022-114 HWS2022-85 Takuma Yabe, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
Sat, Mar 4 AM  HWS
10:00 - 11:05
(43) 10:00-10:25 Importance of Inverters Placement in Ring-Oscilator for Laser Irradiation Detection VLD2022-115 HWS2022-86 Shungo Hayashi (YNU), Junichi Sakamoto (AIST/YNU), Masaki Chikano, Tsutomu Matsumoto (YNU)
(44) 10:25-10:50 Fundamental study of distance spoofing attack against dToF lidar with interference mitigation function VLD2022-116 HWS2022-87 Midori Tomijima, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
  10:50-11:05 Break ( 15 min. )
Sat, Mar 4 AM  HWS
11:05 - 13:30
(45) 11:05-11:30 Clone Resistance of Artifact Metrics: Scanning Probe Lithography Based Clones VLD2022-117 HWS2022-88 Naoki Yoshida, Akira Iwahashi (YNU), Hoga Morihisa, Junko Ohta, Kaoru Sumiya (AIST), Tsutomu Matsumoto (YNU)
(46) 11:30-11:55 Clone Resistance of Artifact Metrics Systems Based on White Light Interferometry and Phase Only Correlation VLD2022-118 HWS2022-89 Akira Iwahashi, Naoki Yoshida, Tsutomu Matsumoto (YNU)
(47) 11:55-12:20 Cloud Based Evaluation of Communication Bandwidth and Tracking Time of Traceable Aggregate Signature Protocols VLD2022-119 HWS2022-90 Koudai Aoyama, Riku Anzai, Junichi Sakamoto, Naoki Yoshida, Tsutomu Matsumoto (Yokohama National Univ.)
  12:20-13:30 Break ( 70 min. )
Sat, Mar 4 PM  HWS
13:30 - 14:45
(48) 13:30-13:55 Threat of EM Information Leakage from Speakerphones Due to IEMI and Suppression Indexes for EMC Countermeasures VLD2022-120 HWS2022-91 Seiya Takano, Yuichi Hayashi (NAIST)
(49) 13:55-14:20 * VLD2022-121 HWS2022-92 Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Nagata Makoto (Kobe Univ.)
(50) 14:20-14:45 Side-channel Information Leakage Resistance Evaluation of Cryptographic Multi- chip Modules VLD2022-122 HWS2022-93 Takumi Matsumaru, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
HWS Technical Committee on Hardware Security (HWS)   [Latest Schedule]
Contact Address Daisuke Fujimoto(NAIST), Hirotake Yamamoto(SSS)
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Masashi IMAI (Hirosaki Univ. )
E--mail: bi-u 
Announcement See also VLD's homepage:

Last modified: 2023-02-27 08:44:31

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