|
|
| Chair |
|
Shinji Kimura |
| Vice Chair |
|
Hirofumi Hamamura |
| Secretary |
|
Yusuke Matsunaga, Toshiyuki Shibuya |
|
|
|
| Chair |
|
Masao Nakaya |
| Vice Chair |
|
Akira Matsuzawa |
| Secretary |
|
Shinji Miyano, Koji Kai |
| Assistant |
|
Yoshiharu Aimoto, Makoto Nagata |
|
|
|
| Chair |
|
Kiyoshi Furuya |
| Vice Chair |
|
Kazuhiko Iwasaki |
| Secretary |
|
Kenji Toda, Toshinori Hosokawa |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Takashi Kambe |
| Secretary |
|
Masato Edahiro, Mitsuhisa Ohnishi, Kiyoharu Hamaguchi |
|
| Conference Date |
Wed, Nov 30, 2005 13:30 - 17:25
Thu, Dec 1, 2005 09:30 - 17:30
Fri, Dec 2, 2005 09:30 - 16:15 |
| Topics |
Design/Verification/Test of VLSI systems, etc. |
| Conference Place |
|
Wed, Nov 30 PM
13:30 - 14:20 |
| (1) |
13:30-14:20 |
[Fellow Memorial Lecture]
Layout CAD and DFM
-- Beginning and Maturity -- |
Takashi Mitsuhashi (Cadence Japan) |
Wed, Nov 30 PM
14:40 - 15:55 |
| (2) |
14:40-15:05 |
40-Gbps 4:1 MUX/1:4 DEMUX in 90-nm standard CMOS technology |
Kouichi Kanda, Daisuke Yamazaki, Takuji Yamamoto, Minoru Horinaka, Junji Ogawa, Hirotaka Tamura, Hiroyuki Onodera (Fujitsu Labs.) |
| (3) |
15:05-15:30 |
Enhancement of an Angular Position Error Measurement Circuit for Rotary Encoders |
Teruo Tamama, , Tadashi Masuda (SIST) |
| (4) |
15:30-15:55 |
Low Power Design for IEEE 802.11 WLAN at the Medium Access Control Layer |
EL Bourichi Adil, Hiroto Yasuura (Kyushu Univ.) |
Wed, Nov 30 PM
16:10 - 17:25 |
| (5) |
16:10-16:35 |
Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition |
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki |
| (6) |
16:35-17:00 |
A Discussion about Timing Signal Design Considering Delay Variation |
Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
| (7) |
17:00-17:25 |
Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation |
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
Thu, Dec 1 AM
09:30 - 10:45 |
| (8) |
09:30-09:55 |
Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure |
Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
| (9) |
09:55-10:20 |
A equidistant transition circuit for detecting path-delay faults |
Hyonsu Cho, Takeo Yoshida (Univ. of the Ryukyus) |
| (10) |
10:20-10:45 |
Reconfigurable Wrapper Design for Multi Clock Domain Cores Under Power Constraints |
Yu Tanaka, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
Thu, Dec 1 AM
11:00 - 12:15 |
| (11) |
11:00-11:25 |
Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule |
Mineo Kaneko (JAIST) |
| (12) |
11:25-11:50 |
A Consideration of Chaining methods on Behavioral Synthesis |
Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) |
| (13) |
11:50-12:15 |
A High-level Synthesis Algorithm Based on Floorplans for Distributed/Shared-Register Architectures |
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
Thu, Dec 1 PM
13:30 - 15:10 |
| (14) |
13:30-13:55 |
Pipelined Bipartite Modular Multiplication |
Marcelo E. Kaihara, Naofumi Takagi (Nagoya Univ.) |
| (15) |
13:55-14:20 |
no title |
Keita Okubo, noname, noname, Takashi Kambe (noname) |
| (16) |
14:20-14:45 |
Consideration on Delay Estimation Methods for Prefix Graphs |
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
| (17) |
14:45-15:10 |
Comparison of power consumption by form of adders |
Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT) |
Thu, Dec 1 PM
15:25 - 17:30 |
| (18) |
15:25-15:50 |
A Study of the Model and the Accuracy of Statistical Timing Analysis |
Izumi Nitta, Katsumi Homma, Toshiyuki Shibuya (Fujitsu Lab.) |
| (19) |
15:50-16:15 |
Fast Interconnect Delay Estimation with Considering Inductance Based on Multiple Regression Analysis |
Kosei Suzuki, Marta D.Anwar, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (20) |
16:15-16:40 |
Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect |
Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) |
| (21) |
16:40-17:05 |
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization |
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
| (22) |
17:05-17:30 |
Floorplan Design for 3D-VLSI |
Hidenori Ohta (Tokyo Univ. of Agri. & Tech.), Toshinori Yamada (Saitama Univ.), Chikaaki Kodama, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. & Tech.) |
Fri, Dec 2 AM
09:30 - 10:45 |
| (23) |
09:30-09:55 |
On Low Capture Power Test Generation for Scan Testing |
Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST) |
| (24) |
09:55-10:20 |
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits |
Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST) |
| (25) |
10:20-10:45 |
A Note on Expansion of Convolutional Compactors on Galois Field |
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
Fri, Dec 2 AM
11:00 - 12:15 |
| (26) |
11:00-11:25 |
Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP |
Kenichi Nishiguchi, Nagisa Ishiura, Masanari Nishimura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Nagoya Univ.), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ.) |
| (27) |
11:25-11:50 |
A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios |
Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) |
| (28) |
11:50-12:15 |
no title |
Kenichi Jyoko, Takahiro Ohguchi, Hirokazu Uetsu, Koji Sakai, noname, Takashi Kambe (noname) |
Fri, Dec 2 PM
13:30 - 15:10 |
| (29) |
13:30-13:55 |
Examinations of Small-World and Scale-Free characteristics in logic circuits |
Toshiaki Miyazaki (Univ. of Aizu) |
| (30) |
13:55-14:20 |
Exact Minimum Factoring via Quantified Boolean Satisfiability |
Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
| (31) |
14:20-14:45 |
An Encoding Method for Rail Outputs in LUT Cascade Emulators |
Shinya Nagayasu, Tsutomu Sasao, Munehiro Matsuura (KIT) |
| (32) |
14:45-15:10 |
A Logic Simulation using an LUT Cascade Emulator |
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) |
Fri, Dec 2 PM
15:25 - 16:15 |
| (33) |
15:25-15:50 |
Efficient contraction of timed signal transition graphs |
Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
| (34) |
15:50-16:15 |
Structural Coverage of Traversed Transitions for Symbolic Model Checking |
Xingwen Xu, Shinji Kimura (Waseda Univ.), Kazunari Horikawa, Takehiko Tsuchiya (Toshiba) |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Yusuke Matsunaga (Kyushu University)
TEL +81-92-583-7621, FAX +81-92-583-1338
E- :      c  cek shu-u |
| Announcement |
You will see the latest information at the below WEB page.
http://www.ieice.org/vld/index.html |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Kunio Uchiyama (Hitachi)
TEL +81-42-323-1111 (etx. 3701), FAX +81-42-327-7737
E-: u  crl   |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
Kenji Toda
AIST, Tsukuba Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568, JAPAN
Information Technology Research Institute
TEL029-861-5840,FAX029-861-5909
E-:k-  aist ,t7   cit n-u |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
|
Last modified: 2005-09-29 18:50:31
|
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