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Chair |
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Shinichi Kawamura (Toshiba) |
Vice Chair |
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Makoto Ikeda (Univ. of Tokyo), Yasuhisa Shimazaki (Renesas Electronics) |
Secretary |
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Hiroki Kunii (SECOM), Takatsugu Ono (Kyushu Univ.) |
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Conference Date |
Fri, Dec 6, 2019 10:00 - 17:00 |
Topics |
Hardware Security Forum 2019 |
Conference Place |
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(1) |
10:00-10:05 |
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(2) |
10:05-10:10 |
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Fri, Dec 6 AM 10:10 - 13:00 |
(3) |
10:10-10:40 |
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(4) |
10:40-11:10 |
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(5) |
11:10-11:40 |
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11:40-13:00 |
Lunch Break ( 80 min. ) |
Fri, Dec 6 PM 13:00 - 13:15 |
(6) |
13:00-13:15 |
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Fri, Dec 6 PM 13:15 - 15:30 |
(7) |
13:15-13:45 |
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(8) |
13:45-14:15 |
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14:15-14:30 |
Break ( 15 min. ) |
(9) |
14:30-15:00 |
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(10) |
15:00-15:30 |
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Fri, Dec 6 PM 15:30 - 17:00 |
(1) |
15:30-15:45 |
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15:45-16:00 |
Break ( 15 min. ) |
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(2) |
16:00-17:00 |
[Poster Presentation]
Comparison of 3 TEEs (Intel SGX, ARM TrustZone, RISC-V Keystone) |
Kuniyasu Suzaki, Akira Tsukamoto (AIST), Kazumoto Kojima (TRASIO), Hoang Trong-Thuc, Akira Moroo (AIST) |
(3) |
16:00-17:00 |
[Poster Presentation]
Workshop Report: RISC-V Workshop Zurich
-- The latest security trends in RISC-V -- |
Shinichi Miyazawa (SECOM) |
(4) |
16:00-17:00 |
[Poster Presentation]
Correlation power analysis and its countermeasure for lightweight ciphers LED and SKINNY implemented in SAKURA-X FPGA |
Hayato Tanaka, Keisuke Iwai, Takashi Matsubara, Takakazu Kurokawa (NDA) |
(5) |
16:00-17:00 |
[Poster Presentation]
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator |
Kota Yoshida, Shunsuke Okura, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.) |
(6) |
16:00-17:00 |
[Poster Presentation]
Fully Homomorphic Encrypted Inference Model of Binarized Neural Network |
Shotaro Sugiyama, Makoto Ikeda (UTokyo) |
(7) |
16:00-17:00 |
[Poster Presentation]
Evaluation of Information Leakage Induced by IEMI from ICs with Multiple Data Communication Lines |
Riho Kawakami, Shugo Kaji (NAIST), Masahiro Kinugawa (NIT, Sendai College), Daisuke Fujimoto, Yu-ichi Hayashi (NAIST) |
(8) |
16:00-17:00 |
[Poster Presentation]
Fundamental evaluation of output bits estimated by changes in internal state of TERO-based TRNG |
Saki Osuka, Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
(9) |
16:00-17:00 |
[Poster Presentation]
Can Coding Prevent 1-bit Instruction Replacement Fault Attacks? |
Shungo Hayashi, Junichi Sakamoto, Tsutomu Matsumoto (YNU) |
(10) |
16:00-17:00 |
[Poster Presentation]
A System for USB Device Identification Based on Electrical Characteristics |
Taku Toyama, Junichi Sakamoto, Naoki Yoshida, Tsutomu Matsumoto (YNU) |
(11) |
16:00-17:00 |
[Poster Presentation]
YNU Double-Spot Laser Station
-- Double-Spot Laser Station that can Set the Irradiation Positions Independently in the Same Field of View -- |
Junichi Sakamoto, Tomoro Suzuki, Tsutomu Matsumoto (YNU) |
(12) |
16:00-17:00 |
[Poster Presentation]
An Evaluation of Pairing Implementation on Virtex-6 with Pipelined Modular Multiplier |
Yota Okuaki, Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) |
(13) |
16:00-17:00 |
[Poster Presentation]
Design of Pairing Processor for Functional Cryptography |
Ryohei Nakayama, Makoto Ikeda (Univ. of Tokyo) |
(14) |
16:00-17:00 |
[Poster Presentation]
A Study of Vulnerability Evaluation Method of Fault Attack on AES Circuit Using Clock Glitch |
Seiki Hara, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) |
(15) |
16:00-17:00 |
[Poster Presentation]
Fundamental study of EM side-channel analysis using electric field distributed on backside of PCB |
Shinpei Wada, Daisuke Fujimoto (NAIST), Naofumi Homma (Tohoku Univ.), Yuichi Hayashi (NAIST) |
Announcement for Speakers |
General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Contact Address and Latest Schedule Information |
HWS |
Technical Committee on Hardware Security (HWS) [Latest Schedule]
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Contact Address |
Hiroki Kunii(SECOM), Takatsugu Ono(Kyushu Univ)
E- :hws- c  |
Last modified: 2019-12-06 14:10:23
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