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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Noriyuki Minegishi (Mitsubishi Electric)
Vice Chair Nozomu Togawa (Waseda Univ.)
Secretary Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu)

Technical Committee on Hardware Security (HWS) [schedule] [select]
Chair Tsutomu Matsumoto (Yokohama National Univ.)
Vice Chair Shinichi Kawamura (Toshiba), Makoto Ikeda (Univ. of Tokyo)
Secretary Noriyuki Miura (Kobe Univ.), Hiroki Kunii (SECOM)

Conference Date Wed, Feb 27, 2019 10:25 - 17:35
Thu, Feb 28, 2019 10:00 - 17:35
Fri, Mar 1, 2019 10:00 - 17:35
Sat, Mar 2, 2019 10:00 - 14:45
Topics Design Technology for System-on-Silicon, Hardware Security, etc. 
Conference Place Okinawa Ken Seinen Kaikan 
Transportation Guide http://www.okiseikan.or.jp/
Sponsors This conference is supported by IEEE CEDA All Japan Joint Chapter.
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on HWS, VLD.

Wed, Feb 27 AM  VLD(1)
10:25 - 11:40
(1) 10:25-10:50 FPGA Implementation of Fully Convolutional Network for Semantic Segmentation VLD2018-93 HWS2018-56 Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech)
(2) 10:50-11:15 Spatial-Separable Convolution: Low memory CNN for FPGA VLD2018-94 HWS2018-57 Akira Jinguji, Masayuki Shimoda, Hiroki Nakahara (titech)
(3) 11:15-11:40 A Case Study on Approximate Multipliers for MNIST CNN VLD2018-95 HWS2018-58 Kenta Shirane, Takahiro Yamamoto (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
  11:40-12:40 Lunch Break ( 60 min. )
Wed, Feb 27 PM  VLD(2)
12:40 - 14:20
(4) 12:40-13:05 Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis VLD2018-96 HWS2018-59 Masato Tatsuoka, Mineo Kaneko (JAIST)
(5) 13:05-13:30 Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA VLD2018-97 HWS2018-60 Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(6) 13:30-13:55 Routing Algorithm to Achieve Circular Wire for SIM-Type SADP VLD2018-98 HWS2018-61 Shun Akatsuka, Kunihiro Fujiyoshi (TUAT)
(7) 13:55-14:20 Set-Pair Routing Algorithm with Selective Pin-Pair Connections VLD2018-99 HWS2018-62 Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
  14:20-14:30 Break ( 10 min. )
Wed, Feb 27 PM  VLD(3)
14:30 - 16:10
(8) 14:30-14:55 Function-level Module Sharing with High-level Synthesis VLD2018-100 HWS2018-63 Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
(9) 14:55-15:20 High-Level Synthesis of the CHStone Benchmark Programs with SDSoC VLD2018-101 HWS2018-64 Takuya Adachi (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
(10) 15:20-15:45 Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework VLD2018-102 HWS2018-65 Masataka Aoki, Yukihide Kohira (Univ. of Aizu)
(11) 15:45-16:10 Timing Correction by Constrained Temperature Dependent Clock Skew VLD2018-103 HWS2018-66 Mineo Kaneko (JAIST)
  16:10-16:20 Break ( 10 min. )
Wed, Feb 27 PM  VLD(4)
16:20 - 17:35
(12) 16:20-16:45 A Battery Degradation aware System Level Battery Management Methodology VLD2018-104 HWS2018-67 Daichi Watari, Ittetsu Taniguchi, Takao Onoye (Osaka Univ.)
(13) 16:45-17:10 Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory VLD2018-105 HWS2018-68 Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
(14) 17:10-17:35 Improvement on DMA Transfer Efficiency by Packet Concatenation VLD2018-106 HWS2018-69 Shoko Ohteru, Saki Hatta, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT)
Thu, Feb 28 AM  VLD(5)
10:00 - 11:40
(15) 10:00-10:25 Thermal transient analysis and evaluation of the heat generation and dissipation in three-dimensional stacked LSI VLD2018-107 HWS2018-70 Ryota Horigome, Kimiyoshi Usami (Shibaura Inst. of Tech.)
(16) 10:25-10:50 Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB VLD2018-108 HWS2018-71 Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)
(17) 10:50-11:15 Single Supply Level Shifter Circuit using body-bias VLD2018-109 HWS2018-72 Yuki Takeyoshi, Kimiyoshi Usame (SIT)
(18) 11:15-11:40 Implementation Technology for the Advanced Wafer Manufacturing Processes on Optical Transmission LSIs VLD2018-110 HWS2018-73 Susumu Hirano, Hideo Yoshida, Kenya Sugihara, Yoshiaki Konishi, Takashi Sugihara, Yoshihiro Ogawa (Mitsubishi Electric)
  11:40-12:40 Lunch Break ( 60 min. )
Thu, Feb 28 PM  VLD(6)
12:40 - 14:20
(19) 12:40-13:05 * VLD2018-111 HWS2018-74 Yuka Aizawa, Masashi Tawada (Waseda Univ.), Yuta Ideguchi, Norifumi Kamiya (NEC), Nozomu Togawa (Waseda Univ.)
(20) 13:05-13:30 High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology VLD2018-112 HWS2018-75 Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(21) 13:30-13:55 Selection of Gaussian Mixture Reduction Methods Using Machine Learning VLD2018-113 HWS2018-76 Haruki Kazama, Shuji Tsukiyama (Chuo Univ.)
(22) 13:55-14:20 Model Compression for ECG Signals Outlier Detection Hardware trained by Sparse Robust Deep Autoencoder VLD2018-114 HWS2018-77 Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech)
  14:20-14:30 Break ( 10 min. )
Thu, Feb 28 PM  VLD(7)
14:30 - 16:10
(23) 14:30-14:55 [Memorial Lecture]
Towards Practical Homomorphic Email Filtering: A Hardware-Accelerated Secure Naive Bayesian Filter VLD2018-115 HWS2018-78
Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
(24) 14:55-15:20 [Memorial Lecture]
Methods for Reducing Power and Area of BDD-based Optical Logic Circuits VLD2018-116 HWS2018-79
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT)
(25) 15:20-15:45 A SPICE Model Parameter Extraction Environment Using Automatic Differentiation VLD2018-117 HWS2018-80 Aoi Ueda (NNCT), Michihiro Shintani (NAIST), Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT), Michiko Inoue (NAIST)
(26) 15:45-16:10 An Algorithm to Determine Circuit Model Parameters for Electric Double-Layer Capacitor VLD2018-118 HWS2018-81 Naoki Kosaka, Shuji Tsukiyama (Chuo Univ.), Kenichi Noto, Takuji Okumura (Komatsu Ltd.)
  16:10-16:20 Break ( 10 min. )
Thu, Feb 28 PM  HWS(1)
16:20 - 17:35
(27) 16:20-16:45 Design of High-Speed Gaussian Sampler Using Micciancio-Walter Algorithm VLD2018-119 HWS2018-82 Keitaro Koga (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo)
(28) 16:45-17:10 Fundamental Study on Individual Identification Method of Electronic Device Using Difference of Radiation Spectrum Caused by Manufacturing/Mounting Variations VLD2018-120 HWS2018-83 Shugo Kaji (NAIST), Masahiro kinugawa (NIT), Daisuke Fujimoto (NAIST), Laurent Sauvage, Jean-Luc Danger (Telecom ParisTech), Yu-ichi Hayashi (NAIST)
(29) 17:10-17:35 Error correction method for PUF utilizing the Pixel Variation in the CMOS Image Sensor VLD2018-121 HWS2018-84 Ryota Ishiki, Masayoshi Shirahata (Ritsumeikan Univ.), Shunsuke Okura (Brillnics), Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Kenichiro Ishikawa, Isao Takayanagi (Brillnics), Takeshi Fujino (Ritsumeikan Univ.)
Fri, Mar 1 AM  VLD(8)
10:00 - 11:40
(30) 10:00-10:25 Synthesis of Full Hardware Implementation of RTOS-Based Systems VLD2018-122 HWS2018-85 Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
(31) 10:25-10:50 A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs VLD2018-123 HWS2018-86 Tatsuki Otake, Hiroshi Saito (UoA)
(32) 10:50-11:15 Reinforcing Generation of Instruction Sequences in Random Testing of Android Virtual Machine VLD2018-124 HWS2018-87 Ryotaro Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.)
(33) 11:15-11:40 Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs VLD2018-125 HWS2018-88 Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.)
  11:40-12:40 Lunch Break ( 60 min. )
Fri, Mar 1 PM  VLD(9)
12:40 - 14:20
(34) 12:40-13:05 On evaluation of an efficient SAT attack algorithm for logic encryption VLD2018-126 HWS2018-89 Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)
(35) 13:05-13:30 A Study on Quantized HOG Calculation suitable for Hardware Implementation VLD2018-127 HWS2018-90 Yusuke Sekiguchi, Yoichi Tomioka, Junji Kitamichi (UoA.)
(36) 13:30-13:55 Energy-Efficient, Small-Scale Multicore Processor towards IoT Edge Computing VLD2018-128 HWS2018-91 Sayuri Onagi, Kaoru Saso, Yuko Hara-Azumi (Tokyo Tech.)
(37) 13:55-14:20 Embedded Systems Designs Using Approximate Computing for Data Clustering Acceleartion VLD2018-129 HWS2018-92 Shun Kimijima, Fransiscus Marcel Satria, Yuko Hara-Azumi (Tokyo Tech.)
  14:20-14:30 Break ( 10 min. )
Fri, Mar 1 PM  HWS(2)
14:30 - 16:10
(38) 14:30-14:55 Integrated Circuit Design and Evaluation of Chip-Package-Board Interactive PUF Based on Wireless Chaos Oscillation VLD2018-130 HWS2018-93 Masanori Takahashi, Makoto Nagata, Noriyuki Miura (Kobe Univ.)
(39) 14:55-15:20 Performance and Security Evaluation of Ring Oscillator PUF Implemented on ASIC VLD2018-131 HWS2018-94 Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(40) 15:20-15:45 An Attack with Linear Model Against Improved Arbiter PUF VLD2018-132 HWS2018-95 Susumu Matsumi, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(41) 15:45-16:10 On Machine Learning Attack Tolerance for PUF-based Device Authentication System VLD2018-133 HWS2018-96 Tomoki Iizuka (UTokyo), Yasuhiro Ogasahara, Toshihiro Katashita, Yohei Hori (AIST), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo)
  16:10-16:20 Break ( 10 min. )
Fri, Mar 1 PM  HWS(3)
16:20 - 17:35
(42) 16:20-16:45 Low-Cost Power Analysis Countermeasures for Unrolled Architecture Implementation PRINCE VLD2018-134 HWS2018-97 Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(43) 16:45-17:10 A Counter Synchronization Method for MAC generation in CAN Communication VLD2018-135 HWS2018-98 Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(44) 17:10-17:35 An Extended of Secure Remote Management Architecture for IoT-device VLD2018-136 HWS2018-99 Masahiro Shiraishi, Hiroki Ito, Keiichi Okabe (NTT)
Sat, Mar 2 AM  HWS(4)
10:00 - 11:15
(45) 10:00-10:25 An ultra-light weight implementation of PRINCE-family cryptographic processor VLD2018-137 HWS2018-100 Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.)
(46) 10:25-10:50 ASIC Chip Implementation and Evaluation of Elliptic Curve Digital Signature Algorithm VLD2018-138 HWS2018-101 Sosuke Sato, Hiroki Yoshida, Kazuki Monta (Kobe Univ.), Takaaki Okidono (ECSEC), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)
(47) 10:50-11:15 A Report on Adoption Rates of Android Devices Implemented Hardware-backed Key Management VLD2018-139 HWS2018-102 Kohei Isobe, Takahito Sakamoto (SECOM)
  11:15-13:05 Lunch Break ( 110 min. )
Sat, Mar 2 PM  HWS(5)
13:05 - 14:45
(48) 13:05-13:30 A study of interference method using flicker noise for a pedestrian detection system VLD2018-140 HWS2018-103 Hirotaka Sakakibara, Kota Yoshida, Masayoshi Shirahata, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ)
(49) 13:30-13:55 An Instrumentation Security Metric for ToF Depth-Image Cameras VLD2018-141 HWS2018-104 Satoru Sakurazawa, Daisuke Fujimoto, Tsutomu Matsumoto (YNU)
(50) 13:55-14:20 A Study of Collision Attacks on Moving Vehicle Equipped with Stereo Vision Camera VLD2018-142 HWS2018-105 Hiroki Nohira, Yasushi Iwata, Naoki Yoshida, Tsutomu Matsumoto (YNU)
(51) 14:20-14:45 Conditions for Successful Attacks on Ultrasonic Range Finder to Output Incorrect Values VLD2018-143 HWS2018-106 Yuya Inoue, Hiroki Nohira, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matumoto (YNU)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Koyo Nitta (NTT)
E-: t 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
HWS Technical Committee on Hardware Security (HWS)   [Latest Schedule]
Contact Address Noriyuki Miura(Kobe University), Hiroki Kunii(SECOM)
E-:hws-c 


Last modified: 2019-02-27 22:32:34


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