IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Vice Chair Minako Ikeda (NTT)
Secretary Daisuke Kanemoto (Osaka Univ.), Makoto Miyamura (NEC)

Technical Committee on Hardware Security (HWS) [schedule] [select]
Chair Yasuhisa Shimazaki (Renesas Electronics)
Vice Chair Makoto Nagata (Kobe Univ.), Daisuke Suzuki (Mitsubishi Electric)
Secretary Junko Takahashi (NTT), Daisuke Fujimotoi (NAIST)

Conference Date Mon, Mar 7, 2022 09:10 - 16:45
Tue, Mar 8, 2022 09:30 - 17:40
Topics Design Technology for System-on-Silicon, Hardware Security, etc. 
Conference Place  
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, HWS.

  09:00-09:10 Opening Address ( 10 min. )
Mon, Mar 7 PM 
09:10 - 10:50
(1) 09:10-09:35 Improved placement-method of standard cells considering parallel routing VLD2021-76 HWS2021-53 Takeru Furuyashiki, Kunihiro Fujiyoshi (TUAT)
(2) 09:35-10:00 Bottleneck Channel Routing to Reduce the Area of Analog VLSI VLD2021-77 HWS2021-54 Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat)
(3) 10:00-10:25 A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis VLD2021-78 HWS2021-55 Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.)
(4) 10:25-10:50 Datapath Synthesis Considering Temperature Dependent Timing Skew VLD2021-79 HWS2021-56 Mineo Kaneko (JAIST)
  10:50-11:00 Break ( 10 min. )
Mon, Mar 7 AM 
11:00 - 12:15
(5) 11:00-11:25 Attribute-based Encryption Acceleration by Pairing Engine Hardware on FPGA VLD2021-80 HWS2021-57 Anawin Opasatian, Makoto Ikeda (EEIS, The University of Tokyo)
(6) 11:25-11:50 Design and Measurement of Crypto Processor for Post Quantum Cryptography CRYSTALS-Kyber VLD2021-81 HWS2021-58 Taishin Shimada, Makoto Ikeda (Univ. of Tokyo)
(7) 11:50-12:15 An efficient scheme of homomorphic encryption for stochastic computing and its performance evaluation VLD2021-82 HWS2021-59 Ryusuke Koseki, Rei Ueno, Akira Ito, Naofumi Homma (Tohoku Univ.)
  12:15-13:15 Lunch Break ( 60 min. )
Mon, Mar 7 PM 
13:15 - 14:55
(8) 13:15-13:40 [Memorial Lecture]
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers VLD2021-83 HWS2021-60
Lingxiao Hou, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.)
(9) 13:40-14:05 [Memorial Lecture]
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification VLD2021-84 HWS2021-61
Dehua Liang, Jun Shiomi, Noriyuki Miura (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.)
(10) 14:05-14:30 Measurement Results of Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations VLD2021-85 HWS2021-62 Yuki Abe, Kazutoshi Kobayashi (KIT), Hiroyuki Ochi (Ritsumeikan Univ.)
(11) 14:30-14:55 MTJ-based non-volatile SRAM circuit with Approximate Image-data Storing for energy saving VLD2021-86 HWS2021-63 Hisato Miyauchi, Kimiyoshi Usami (SIT)
  14:55-15:05 Break ( 10 min. )
Mon, Mar 7 PM 
15:05 - 16:45
(12) 15:05-15:30 Low-Energy and Fast Inference Method for Spiking Neural Networks Using Dynamic Threshold Adjustment VLD2021-87 HWS2021-64 Takehiro Habara, Hiromitsu Awano (Kyoto Univ.)
(13) 15:30-15:55 High-throughput In-Memory Accelerator for Binarized Neural Network based on 8T-SRAM VLD2021-88 HWS2021-65 Hiroto Tagata, Hiromitsu Awano (Kyoto Univ.)
(14) 15:55-16:20 A Force-Haptic Guided Control System for Smooth Manipulation of Flexible Objects by Teleoperated Robots VLD2021-89 HWS2021-66 Satoko Iida, Hiromitu Awano (Kyoto Univ.)
(15) 16:20-16:45 AmoebaSAT-based Efficient Accelerator for Autonomous Driving Application VLD2021-90 HWS2021-67 Yusuke Inuma, Yuko Hara-Azumi (Tokyo Tech)
Tue, Mar 8 AM 
09:30 - 10:45
(16) 09:30-09:55 A Study on Interface Circuits Using Click Element Between Synchronous-asynchronous Domains VLD2021-91 HWS2021-68 Shogo Semba, Hiroshi Saito (UoA)
(17) 09:55-10:20 Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment VLD2021-92 HWS2021-69 Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology)
(18) 10:20-10:45 Evaluation of leakage-based LR-PUF's resistance to machine learning attacks VLD2021-93 HWS2021-70 Tomoaki Oikawa, Kimiyoshi Usami (SIT)
  10:45-11:00 Break ( 15 min. )
Tue, Mar 8 AM 
11:00 - 11:50
(19) 11:00-11:25 Evaluation of a Lightweight Cryptographic Finalist on SROS2 VLD2021-94 HWS2021-71 Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(20) 11:25-11:50 A Method for Automatic Test Pattern Generation using an SMT Solver for HDL Code VLD2021-95 HWS2021-72 Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuta Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue (NICT)
  11:50-13:00 Lunch Break ( 70 min. )
Tue, Mar 8 PM 
13:00 - 14:40
(21) 13:00-13:25 Implementation Evaluation of Glitch PUF Using a Low-Latency Cryptography MANTIS VLD2021-96 HWS2021-73 Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(22) 13:25-13:50 A Study on Small Area Circuits for CMOS Image Sensors with Message Authentication Codes (1)
-- Drive Circuit and Pixel Array Configuration --
VLD2021-97 HWS2021-74
Yoshihiro Akamatsu, Hiroaki Ogawa, Tatsuya Oyama, Hayato Tatsuno, Yu Sekioka, Shunsuke Okura, Takeshi Fujino (Ritsumeikan Univ)
(23) 13:50-14:15 A Study on Small Area Circuits for CMOS Image Sensor with Message Authentication codes (2)
-- Code generation circuit --
VLD2021-98 HWS2021-75
Yu Sekioka, Hiroaki Ogawa, Hayato Tatsuno, Tatsuya Oyama, Yoshihiro Akamatsu, Shunsuke Okura, Takeshi Fujino (Ritsumeikan Univ)
(24) 14:15-14:40 A Study on Security Evaluation of COSO-based TRNG VLD2021-99 HWS2021-76 Ryuichi Minagawa, Kotaro Hayashi, Naoya Torii (Soka Univ)
  14:40-14:55 Break ( 15 min. )
Tue, Mar 8 PM 
14:55 - 16:35
(25) 14:55-15:20 Evaluation of Side-channel Leaks Specific to Unrolled AES Hardware VLD2021-100 HWS2021-77 Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.)
(26) 15:20-15:45 Bypassing Isolated Execution on RISC-V Keystone using Fault Injection VLD2021-101 HWS2021-78 Shoei Nashimoto, Daisuke Suzuki (Mitsubishi Electric), Rei Ueno, Naofumi Homma (Tohoku Univ.)
(27) 15:45-16:10 Evaluation Method for EM Information Leakage from Speakerphone Using Voice Frequency Spectrum Analysis VLD2021-102 HWS2021-79 Hiroyuki Ueda, Seiya Takano, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
(28) 16:10-16:35 Fundamental Evaluation Method for EM Information Leakage Caused by Hardware Trojans on Signal Cables
-- Impact of Modulation Factor and Emission Intensity --
VLD2021-103 HWS2021-80
Taiga Yukawa, Shugo Kaji, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
  16:35-16:50 Break ( 15 min. )
Tue, Mar 8 PM 
16:50 - 17:40
(29) 16:50-17:15 Physical Spoofing Attack on LiDAR-based Object Detection and Its Demonstration VLD2021-104 HWS2021-81 Yuki Fukatsu, Ryuuya Ichinose, Shinsei Ueda, Ataru Kubo, Naoki Yoshida, Tsutomu Matsumoto (Yokohama National Univ.)
(30) 17:15-17:40 Development of a Test Environment for Attack-Resistance Evaluation of Matrix Direct ToF Lidar VLD2021-105 HWS2021-82 Masato Suzuki, Daisuke Fujimoto, Yuichi Hayashi (NAIST)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Daisuke KANEMOTO (Osaka Univ. )
E-: deeieng-u 
Announcement See also VLD's homepage:
HWS Technical Committee on Hardware Security (HWS)   [Latest Schedule]
Contact Address Junko Takahashi(NTT)

Last modified: 2022-03-01 10:46:33

Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.

[Presentation and Participation FAQ] (in Japanese)
[Cover and Index of IEICE Technical Report by Issue]

[Return to VLD Schedule Page]   /   [Return to HWS Schedule Page]   /  
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan