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Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Nobuyasu Kanekawa (Hitachi)
Vice Chair Michiko Inoue (NAIST)
Secretary Koji Iwata (RTRI), Masayoshi Yoshimura (Kyoto Sangyo Univ.)

Conference Date Tue, Jun 16, 2015 14:10 - 16:50
Topics Reliable design and Test, etc. 
Conference Place  
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Tue, Jun 16 PM 
14:10 - 16:50
(1) 14:10-14:35 A test data reduction method based on scan slice on BAST DC2015-16 Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
(2) 14:35-15:00 Study on Fast Bridge Fault Test Generation Based on Critical Area DC2015-17 Masayuki Arai (Nihon Univ.), Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
(3) 15:00-15:25 A Method to Identify High Test Power Areas in Layout Design DC2015-18 Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech)
  15:25-15:35 Break ( 10 min. )
(4) 15:35-16:00 A Study on Function Test of Latch-based Asynchronous Pipeline Circuits DC2015-19 Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)
(5) 16:00-16:25 Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models DC2015-20 Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)
(6) 16:25-16:50 Using binary decision diagrams for constraint handling in test case generation DC2015-21 Tatsuhiro Tsuchiya (Osaka Univ.)

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General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

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DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
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