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Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Tsutomu Yoshinaga (Univ. of Electro-Comm.)
Vice Chair Akira Asato (Fujitsu), Yasuhiko Nakajima (NAIST)
Secretary Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Electro-Comm.)
Assistant Hiroaki Inoue (NEC), Takeshi Ohkawa (Utsunomiya Univ.)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Nobuyasu Kanekawa (Hitachi)
Vice Chair Michiko Inoue (NAIST)
Secretary Koji Iwata (RTRI), Tatsuhiro Tsuthiya (Osaka Univ.)

Conference Date Fri, Apr 17, 2015 09:00 - 17:30
Conference Place  
Transportation Guide
Prof. Satoshi Fukumoto
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Fri, Apr 17 AM 
09:00 - 10:15
(1) 09:00-09:25 Redundant Configuration on FPGA with Rejuvenation for Real Time Applications CPSY2015-1 DC2015-1 Aromhack Saysanasongkham, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
(2) 09:25-09:50 Off-loading to PEACH2 of Gravitational Calculation CPSY2015-2 DC2015-2 Chiharu Tsuruta, Takuya Kuhara (Keio univ.), Miki Yohei (Univ. of Tsukuba), Hideharu Amano (Keio univ.)
(3) 09:50-10:15 A Proposal of Time-Lag-Less n-Fault-Tolerant Control System CPSY2015-3 DC2015-3 Hitoshi Iwai
  10:15-10:25 Break ( 10 min. )
Fri, Apr 17 AM 
10:25 - 11:40
(4) 10:25-10:50 3D Shared Bus Architecture Using Inductive-Coupling Interconnect CPSY2015-4 DC2015-4 Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano (Keio Univ.)
(5) 10:50-11:15 Design and Implementation of FPGA-based Sorting Accelerator CPSY2015-5 DC2015-5 Ryohei Kobayashi, Kenji Kise (Tokyo Tech)
(6) 11:15-11:40 An IP-NoC Translator for Connecting NoCs and Internet CPSY2015-6 DC2015-6 Naoaki Kashiwagi, Hiroki Matsutani (Keio Univ.)
  11:40-13:00 Lunch Break ( 80 min. )
Fri, Apr 17 PM 
13:00 - 14:40
(7) 13:00-13:25 CGRA in Cache for Graph Applications CPSY2015-7 DC2015-7 Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)
(8) 13:25-13:50 A study of processor architecture suited for intelligent sensing system CPSY2015-8 DC2015-8 Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST)
(9) 13:50-14:15 Near Memory Processing Architecture for High Performance Atypical Applications CPSY2015-9 DC2015-9 Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)
(10) 14:15-14:40 Parallel Processor Architecture based on Small World Connection CPSY2015-10 DC2015-10 Hideki Mori (Meiji Univ.), Minoru Uehara, Katsuyoshi Matsumoto (Toyo Univ.)
  14:40-14:50 Break ( 10 min. )
Fri, Apr 17 PM 
14:50 - 15:40
(11) 14:50-15:40 [Special Invited Talk]
On Hardware for high-speed pattern matching CPSY2015-11 DC2015-11
Tsutomu Sasao (Meiji Univ.)
  15:40-15:50 Break ( 10 min. )
Fri, Apr 17 PM 
15:50 - 17:30
(12) 15:50-16:15 A parallel-operation-oriented FPGA architecture CPSY2015-12 DC2015-12 Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
(13) 16:15-16:40 A Case Study on Prototyping Cloud based IoT devices CPSY2015-13 DC2015-13 Minoru Uehara (Toyo Univ.)
(14) 16:40-17:05 Frequency Domain aware Power Analysis based on Two Steps Hierarchal Alignment Method CPSY2015-14 DC2015-14 Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(15) 17:05-17:30 Prototyping of GPS-based Item Finder System CPSY2015-15 DC2015-15 Soichiro Kanagawa, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Akira ASATO (FUJITSU)
TEL +81-44-754-3233, FAX +81-44-754-3214
E-: a 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address  

Last modified: 2015-04-09 13:40:50

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