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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2009-04-14 10:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)  ICD2009-6 |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] | ICD2009-6 pp.27-32 |
| VLD | 2009-03-12 13:00 |
Okinawa | Emulation of Sequential Circuits by a Parallel Branching Program Machine Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145 |
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs) and a programmable in... [more] |
VLD2008-145 pp.111-116 |
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| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 16:30 |
Osaka | Shoushin Kaikan | A Low-Power Full-HD H.264 High-Profile Codec Based on a Heterogeneous Multiprocessor Architecture Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda (Renesas Tech Corp.), Koji Hosogi, Hiroaki Nakata, Masakazu Ehama (Hitachi Ltd.), Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe (Renesas Tech Corp.) ICD2008-148 |
A video-size-scalable H.264 High-Profile codec including 19 application-specific CPUs for extensibility to multiple stan... [more] | ICD2008-148 pp.111-116 |
| ICD | 2008-12-12 16:35 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128 |
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] | ICD2008-128 pp.137-142 |
| AP, RCS (Joint) |
2008-11-19 13:25 |
Ishikawa | Kanazawa Institute of Technology | Adjacent channel rejection techniques for the IEEE802.11a/g OFDM system
-- For multi-channel mesh network systems -- Minoru Kubo, Kazuyuki Takada, Takashi Okubo, Keisuke Furumi, Hiroshi Nogami, Hiroyasu Tominaga (Renesas Technology) RCS2008-131 |
IEEE802.11a/g wireless LAN system is greatly widespread. The number of allowed frequency channels are limited in each 2.... [more] | RCS2008-131 pp.7-12 |
| SDM [detail] | 2008-11-14 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
[Invited]Robust Design of Embedded SRAM on Deep-submicron Technology Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178 |
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] | SDM2008-178 pp.55-60 |
| CAS, MSS | 2008-11-07 13:00 |
Osaka | Osaka University | (4n-3)-bit representation of rectangular drawings or floorplans Toshihiko Takahashi, Ryo Fujimaki (Niigata Univ.), Youhei Inoue (Renesas Technology) CAS2008-57 CST2008-35 |
[more] | CAS2008-57 CST2008-35 pp.71-76 |
| CPSY | 2008-10-31 13:15 |
Hiroshima | Hiroshima City Univ. | [Special Invited Talk]
System LSI Device "MX-G" with Matrix Type Massively Parallel Processor
-- MX core massively parallel processor achives 17GOPS at 168MHz for low-power and high-speed execution of sophisticates image processing tasks -- Takeshi Nakamura (Renesas) CPSY2008-32 |
[more] | CPSY2008-32 pp.19-22 |
| SDM | 2008-10-10 13:00 |
Miyagi | Tohoku Univ. | The Application Property of B18H22 Implantation for Millisecond Annealing Yoji Kawasaki, Seiichi Endo, Masashi Kitazawa, Yoshiki Maruyama, Tomohiro Yamashita, Takashi Kuroi, Hidefumi Yoshimura, Masahiro Yoneda (Renesas) SDM2008-161 |
We investigated the application properties of cluster implantation for milli-second annealing processing. We successful... [more] | SDM2008-161 pp.37-40 |
| VLD | 2008-09-29 13:30 |
Ishikawa | [Invited Talk]
Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) VLD2008-47 |
[more] | VLD2008-47 pp.1-6 |
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| ICD, SDM | 2008-07-17 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41 |
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] | SDM2008-131 ICD2008-41 pp.17-22 |
| ICD, SDM | 2008-07-17 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46 |
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] | SDM2008-136 ICD2008-46 pp.47-52 |
| VLD, CAS, SIP | 2008-06-27 11:15 |
Hokkaido | Hokkaido Univ. | An asymptotic estimate of the numbers of rectangular drawings or floorplans Ryo Fujimaki (Niigata Univ.), Youhei Inoue (Renesas Technology), Toshihiko Takahashi (Niigata Univ.) CAS2008-25 VLD2008-38 SIP2008-59 |
A subdivision of a rectangle into rectangular faces with horizontal and vertical line segments is called rectangular d... [more] |
CAS2008-25 VLD2008-38 SIP2008-59 pp.37-41 |
| DC | 2008-06-20 16:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Note on Hardware Overhead and Fault Location for Memory BIST Masayuki Arai, Kentaro Osawa, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao (Renesas) DC2008-18 |
[more] | DC2008-18 pp.41-46 |
| SIS | 2008-06-13 12:50 |
Hokkaido | Application of the massively parallel embedded processor (MX) to real-time image processing Hiroyuki Yamasaki, Takeaki Sugimura, Hideyuki Noda, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) SIS2008-20 |
We developed the massively parallel embedded processor core (MX core) for the SoC(System on Chip) building in as an acce... [more] | SIS2008-20 pp.33-38 |
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| ICD, IPSJ-ARC | 2008-05-13 10:30 |
Tokyo | An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) |
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] | ICD2008-20 pp.19-24 |
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| ICD, IPSJ-ARC | 2008-05-14 09:30 |
Tokyo | Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas) ICD2008-26 |
A multicore SoC has been developed for various applications (recognition, inference, measurement, control and security) ... [more] | ICD2008-26 pp.45-50 |
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| ICD, IPSJ-ARC | 2008-05-14 10:00 |
Tokyo | Multicore Debug Function for Embedded Processor Jun Sakiyama, Makoto Saen (Hitachi, Ltd.), Takehiro Shimizu (Renesas Technology Corp.) |
[more] | ||
| ICD | 2008-04-17 10:15 |
Tokyo | [Invited Talk]
65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2 |
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] | ICD2008-2 pp.7-12 |
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| ICD | 2008-04-18 10:25 |
Tokyo | [Invited Talk]
* Shinji Kawai, Akira Hosogane, Shigehiro Kuge, Toshihiro Abe, Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi (Renesas) ICD2008-9 |
This paper describe an 8kB EEPROM-Emulation DataFLASH (E2FLASH) that replaces on-board EEPROM using dual-channel NOR-typ... [more] | ICD2008-9 pp.45-50 |
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