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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ET | 2021-03-06 15:00 |
Online | Online | Comparison of Learning State between Visual Programming Language and Text Programming Language Katsuyuki Umezawa (Shonan Inst. of Tech.), Takashi Ishida (Takasaki City Univ. of Economics), Makoto Nakazawa (Junior College of Aizu), Shigeichi Hirasawa (Waseda Univ.)  ET2020-72 |
In recent years, programming beginners have begun to use visual programming languages such as Scratch. After that, they ... [more] | ET2020-72 pp.115-120 |
| OPE, OCS, OFT (Joint) [detail] |
2021-02-19 17:00 |
Online | Online | Power Consumption of Optical Repeater in Multicore Fiber Link System Hirotaka Ono (Shonan Inst. of Tech.), Makoto Yamada (Osaka Pref. Univ.) OCS2020-48 OPE2020-97 |
[more] | OCS2020-48 OPE2020-97 pp.26-31(OCS), pp.100-105(OPE) |
| CAS, ICTSSL | 2021-01-29 10:10 |
Online | Online | Consideration of Switching by Chaotic Neurodynamics for Asymmetric TSPs by using Hidden Markov Model Tomoya Matsuno, Toshihiro Tachibana (Shonan Inst. of Tech.), Masaharu Adachi (Tokyo Denki Univ.) CAS2020-59 ICTSSL2020-44 |
Several methods for solving the asymmetric traveling salesman problem using chaotic neural networks is proposed by Tachi... [more] | CAS2020-59 ICTSSL2020-44 pp.107-110 |
| CAS, ICTSSL | 2021-01-29 10:30 |
Online | Online | A Method for Solving Traveling Salesman Problems Using Switching of Crossover by Chaotic Neurodynamics Masayuki Kashiwagi, Tomoki Ishizawa, Toshihiro Tashibana (Shonan Inst. of Tech.) CAS2020-60 ICTSSL2020-45 |
In this paper, we solve traveling salesman problems using genetic algorithm. The genetic algorithm is a heuristic method... [more] | CAS2020-60 ICTSSL2020-45 pp.111-114 |
| MW (2nd) |
2020-05-13 - 2020-05-15 |
Overseas | CU, Bangkok, Thailand (Postponed) |
CMOS Vector-Sum Phase Shifter With Novel Vector Summer Takana Kaho (Shonan Inst. of Tech.), Kotaro Takamiya, Ramesh Pokharel Kumar (Kyushu University) |
A quasi-millimeter CMOS phase shifter which employed a vector sum structure is designed. It consists of an active balun,... [more] | |
| ITE-HI, IE, ITS, ITE-MMS, ITE-ME, ITE-AIT [detail] | 2020-02-27 10:30 |
Hokkaido | Hokkaido Univ. (Cancelled but technical report was issued) |
A study of autonomous control method for UAV under non-GPS environment using relation between flight command and 3D moving vector Miku Kawaguchi (Aichi Pref. Univ.), Isao Miyagawa (Shonan Inst. of Tech. Univ.), Kazuhito Murakami (Aichi Pref. Univ.) |
[more] | |
| NLP, NC (Joint) |
2020-01-24 13:10 |
Okinawa | Miyakojima Marine Terminal | Optimization of CMOS operational amplifier using MOGA Hitoshi Kubo (Shizuoka Univ.), Hiroshi Ninomiya (Shonan Inst. of Tech.), Hideki Asai (Shizuoka Univ.) NLP2019-93 |
Multi-Objective Genetic Algorithm (MOGA) is an extended version of Genetic Algorithm (GA) for problems with multiple obj... [more] | NLP2019-93 pp.45-48 |
| SDM | 2019-11-07 16:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study of stacked type logic circuit with fabrication technology of 3D flash memory.
-- Design of full adder and low power. -- Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2019-73 |
[more] | SDM2019-73 pp.21-25 |
| SDM, ED, CPM | 2019-05-16 13:50 |
Shizuoka | Shizuoka Univ. (Hamamatsu) | Study of new stacked full adder circuit with fabrication technology of 3D flash memory. Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ED2019-12 CPM2019-3 SDM2019-10 |
[more] | ED2019-12 CPM2019-3 SDM2019-10 pp.9-13 |
| VLD, IPSJ-SLDM | 2019-05-15 15:00 |
Tokyo | Ookayama Campus, Tokyo Institute of Technology | Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2019-3 |
[more] | VLD2019-3 pp.19-23 |
| RECONF | 2019-05-09 14:10 |
Tokyo | Tokyo Tech Front | Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory. Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) RECONF2019-4 |
[more] | RECONF2019-4 pp.17-21 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 14:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Study of stacked full adder circuit with fabrication technology of 3D flash memory Fumiya Suzuki, Sigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2018-77 CPSY2018-87 RECONF2018-51 |
[more] | VLD2018-77 CPSY2018-87 RECONF2018-51 pp.31-35 |
| ICD, CPSY, CAS | 2018-12-21 15:25 |
Okinawa | Surveying Function of Tourism Assistance Apps in Fujisawa Area Toshihiro Tachibana, Hikaru Habuto, Shogo Tanaka, Tomohiro Chosa, Kei Watanabe, Takashi Satake (Shonan Inst. of Tech.) CAS2018-83 ICD2018-67 CPSY2018-49 |
Fujisawa City, Kanagawa Prefecture is the central city of Shonan area. It has sightseeing resources, including Enoshima ... [more] | CAS2018-83 ICD2018-67 CPSY2018-49 pp.25-30 |
|
| ICD, CPSY, CAS | 2018-12-23 13:20 |
Okinawa | A Study on Input Method of Language in VR Shopping Mall Application Masayoshi Kawasaki, Toshihiro Tachibana, Kaya Nagasawa (Shonan Inst. of Tech.) CAS2018-108 ICD2018-92 CPSY2018-74 |
In recent years, virtual reality (VR) and its related technology are one of expected technologies. In particular, the VR... [more] | CAS2018-108 ICD2018-92 CPSY2018-74 pp.115-118 |
|
| IA, IN (Joint) |
2018-12-14 15:05 |
Hiroshima | Hiroshima Univ. | A Structured Overlay Network Based on a Proximity-aware Distributed Line Graph Youki Shiraishi (NAIST), Akiko Manada (Shonan Inst. of Tech.), Yuzo Taenaka, Youki Kadobayashi (NAIST) IA2018-51 |
A distributed line graph (DLG) is a technique for designing a structured overlay network based on an arbitrary regular g... [more] | IA2018-51 pp.71-77 |
| SDM, ICD, ITE-IST [detail] | 2018-08-08 15:00 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | Study of new stacked type logic circuit with fabrication technology of 3D NAND flash memory
-- Comparison with conventional LUT scheme, and planar typescheme -- Fumiya Suzuki, Sigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2018-43 ICD2018-30 |
Novel new stacked type logic circuit with fabrication technology of 3D flash memory has been newly proposed. Also, These... [more] | SDM2018-43 ICD2018-30 pp.95-100 |
| CAS, SIP, MSS, VLD | 2018-06-15 09:20 |
Hokkaido | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) | A study on cyclic coordinates of multirotor equations Kaito Isogai, Munenari Sako, Hideo Nakano, Hideaki Okazaki (Shonan Inst. of Tech.) CAS2018-19 VLD2018-22 SIP2018-39 MSS2018-19 |
We discuss equations and motions of multirotors. First we introduce the definitions and theorems for multirotor operatin... [more] | CAS2018-19 VLD2018-22 SIP2018-39 MSS2018-19 pp.99-104 |
| CAS, SIP, MSS, VLD | 2018-06-15 12:25 |
Hokkaido | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) | [Panel Discussion]
The role of System and Signal Processing Subsociety
-- The roadmaps of groups and subsociety Part 1 -- Satoshi Yamane (Kanazawa Univ.), Hideaki Okazaki (Shonan Inst. of Tech.), Noriyuki Minegishi (Mitsubishi Electric), Shogo Muramatsu (Niigata Univ.), Morikazu Nakamura (Univ. of the Ryukyus) CAS2018-25 VLD2018-28 SIP2018-45 MSS2018-25 |
The four technical committees CAS, VLD, SIP, and MSS of System and Signal Processing Subsociety holds joint workshop sin... [more] | CAS2018-25 VLD2018-28 SIP2018-45 MSS2018-25 p.129 |
| MSS, NLP (Joint) |
2018-03-14 15:20 |
Osaka | Method for Solving Asymmetric Traveling Salesman Problems by Dynamically Changes the Number of Cities Consider as One City Toshihiro Tachibana (Shonan Inst. of Tech.), Masaharu Adachi (Tokyo Denki Univ.) NLP2017-113 |
In this paper, the authors extend a proposed method for asymmetric traveling salesman problems. Asymmetric traveling sal... [more] | NLP2017-113 pp.61-66 |
|
| RECONF | 2017-09-25 15:25 |
Tokyo | DWANGO Co., Ltd. | Proplsal of reconfigurable system LSI with BiCS technology
-- Application to combination logic, FF, CMOS circuit and FPGA -- Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shouto Tamai (Oi Electric), Takumi Sato (Japan Business Systems) RECONF2017-28 |
[more] | RECONF2017-28 pp.37-42 |
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