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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2017-08-02
13:00		 Hokkaido Hokkaido-Univ. Multimedia Education Bldg. [Invited Talk] A 0.7V 12b 160MS/s 12.8fJ/conv. Calibration-free Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Fururta, Akihide Sai, Tetsuro Itakura (Toshiba) SDM2017-46 ICD2017-34		  [more] SDM2017-46 ICD2017-34
pp.115-116
ICD, ITE-IST 2014-07-03
10:50		 Shimane Izumo-shi (Shimane) A 4-GS/s 5-bit Flash ADC with Dynamic pre-amplifier
Junya Matsuno, Masanori Furuta, Tetsuro Itakura (Toshiba) ICD2014-21		  [more] ICD2014-21
pp.13-16
ICD, ITE-IST 2013-07-05
14:25		 Hokkaido San Refre Hakodate A 1.0-V 12-bit Digitally Calibrated SAR ADC Using Hybrid DAC Technique
Masanori Furuta, Hirotomo Ishii, Tomohiko Sugimoto, Toru Okawa, Masazumi Shiochi, Tetsuro Itakura (Toshiba) ICD2013-39		 A 1.0-V, 12-bit, 80-MS/s two time-interleaved successive
approximation register (SAR) ADC with 1.2-V differential
full... [more]		 ICD2013-39
pp.93-96
CAS, CS, SIP 2012-03-08
13:45		 Niigata The University of Niigata A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique
Masanori Furuta, Taichi Ogawa, Tetsuro Itakura (Toshiba) CAS2011-128 SIP2011-148 CS2011-120		 An eight-channel time-interleaved ADC with individual reference voltage buffers is presented. Each channel consists of b... [more] CAS2011-128 SIP2011-148 CS2011-120
pp.121-124
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