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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 31  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
MSS, CAS, SIP, VLD 2023-07-07
13:30
Hokkaido
(Primary: On-site, Secondary: Online)
CAS2023-23 VLD2023-23 SIP2023-39 MSS2023-23 Quantum computers are next-generation computers that perform massively parallel calculations using the principles of qua... [more] CAS2023-23 VLD2023-23 SIP2023-39 MSS2023-23
pp.113-118
HWS, VLD 2023-03-02
09:55
Okinawa
(Primary: On-site, Secondary: Online)
Implementation of power-outage tolerant VLSI system using asynchronous circuits
Masashi Imai (Hirosaki Univ.) VLD2022-86 HWS2022-57
Re-initialization free systems which contain nonvolatile memory have been proposed in order to cope with power-outage. H... [more] VLD2022-86 HWS2022-57
pp.79-84
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-28
13:05
Kumamoto  
(Primary: On-site, Secondary: Online)
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM
Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII) VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42
An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of ver... [more] VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42
pp.1-6
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
17:05
Kumamoto  
(Primary: On-site, Secondary: Online)
Error detection and countermeasures caused by hardware trojan inserted computers
Takuro Kasai, Masashi Imai (Hirosaki Univ.) VLD2022-55 ICD2022-72 DC2022-71 RECONF2022-78
In recent years, the threat of hardware Trojans has become a serious problem. However, due to the nature of hardware Tro... [more] VLD2022-55 ICD2022-72 DC2022-71 RECONF2022-78
pp.206-211
HWS, ICD [detail] 2019-11-01
16:00
Osaka DNP Namba SS Bld. A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits
Hikaru Inafune, Masashi Imai (Hirosaki Univ.) HWS2019-63 ICD2019-24
There are typically two timing methods in VLSI designs known as
synchronous circuits which use a global clock and async... [more]
HWS2019-63 ICD2019-24
pp.35-40
HWS
(2nd)
2018-12-13
16:10
Tokyo Tokyo Univ. Takeda Bldg. Takeda Hall [Poster Presentation] Hardware Trojan Attack and Countermeasures in Bundle-Data Asynchronous Circuits
Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)
(Advance abstract in Japanese is available) [more]
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2018-07-30
17:00
Kumamoto Kumamoto City International Center An Efficient Implementation Method and Development of Demonstration Environment for Byzantine Fault Tolerant Systems
Masashi Imai, Takeru Nanao, Yudai Ishikawa, Koutaro Inaba (Hirosaki Univ.) DC2018-15
Threats for mission critical systems increase every year. Traditionally, the target fault model of fault–tolerant system... [more] DC2018-15
pp.13-18
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-26
14:00
Akita Akita Atorion-Building (Akita) A Study on Implementation Method of Byzantine Fault Tolerant Systems
Takeru Nanao, Yudai Ishikawa, Masashi Imai (Hirosaki Univ.) DC2017-17
A fault tolerant system does not cause a failure even if a fault occurs. The algorithm OM has been proposed as a basic B... [more] DC2017-17
pp.7-12
HWS
(2nd)
2017-06-12
17:15
Aomori Hirosaki University Hardware Trojan Insertion into Asynchronous On-chip Network Router
Koutaro Inaba, Masashi Imai (Hirosaki Univ.)
(Advance abstract in Japanese is available) [more]
VLD, CAS, MSS, SIP 2016-06-17
15:10
Aomori Hirosaki Shiritsu Kanko-kan Clock Distribution Network with Multiple Source Buffers for Stacked Chips
Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31
pp.167-172
VLD, CAS, MSS, SIP 2016-06-17
15:30
Aomori Hirosaki Shiritsu Kanko-kan Thermal Analysis in 3D ICs
Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32
Three-dimensional integrated circuits (3D ICs) lead to higher power densities than 2D ICs because of the stacking of mul... [more] CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32
pp.173-178
VLD, CAS, MSS, SIP 2016-06-17
15:50
Aomori Hirosaki Shiritsu Kanko-kan A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
A bit flip caused by voltage fluctuation, soft errors, and hardware Trojans becomes one of serious issues in the modern ... [more] CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
pp.179-184
VLD, CAS, MSS, SIP 2016-06-17
16:10
Aomori Hirosaki Shiritsu Kanko-kan Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements
Daiki Toyoshima, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34
Asynchronous bundled-data transfer circuits use delay elements as a strobe signal which indicates the stable state of th... [more] CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34
pp.185-190
VLD 2016-02-29
14:20
Okinawa Okinawa Seinen Kaikan Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme
Hiroshi Saito (Univ. Aizu), Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2015-113
In this paper, we propose a task allocation method for multi-core systems with the Duplication with
Temporary Triple Mo... [more]
VLD2015-113
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
13:45
Nagasaki Nagasaki Kinro Fukushi Kaikan Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-67 DC2015-63
In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequenc... [more] VLD2015-67 DC2015-63
pp.189-194
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-68 DC2015-64
In synchronous circuits, peak currents flow at a constant frequency since a global clock signal which is a timing signal... [more] VLD2015-68 DC2015-64
pp.195-200
DC 2015-06-16
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. A Study on Function Test of Latch-based Asynchronous Pipeline Circuits
Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] DC2015-19
pp.19-24
DC 2015-06-16
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) DC2015-20
In embedded systems, multiple core system is a promising architecture not only for performance improvement, but also for... [more] DC2015-20
pp.25-30
CPSY, DC 2014-04-25
14:00
Tokyo   Construction of Design Environment for Asynchronous Circuits using DDL Cell Library
Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] CPSY2014-2 DC2014-2
pp.3-8
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-07
10:55
Aomori   Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2013-47 ICD2013-71 IE2013-47
There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-p... [more] VLD2013-47 ICD2013-71 IE2013-47
pp.7-12
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