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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 14 of 14  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
PN 2021-03-02
14:30
Online Online RSA-RL: Reinforcement Learning Framework for Routing and Spectrum Assignment in Optical Networks
Masayuki Shimoda, Takafumi Tanaka (NTT) PN2020-57
 [more] PN2020-57
pp.88-91
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
17:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks
Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (Titech) VLD2019-65 CPSY2019-63 RECONF2019-55
A convolutional neural network (CNN) is one of the most successful neural networks and widely used for computer vision t... [more] VLD2019-65 CPSY2019-63 RECONF2019-55
pp.67-72
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
17:45
Kanagawa Raiosha, Hiyoshi Campus, Keio University An FPGA Implementation of Monocular Depth Estimation
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) VLD2019-66 CPSY2019-64 RECONF2019-56
Among a lot of image recognition applications, Convolutional Neural Network (CNN) has gained high accuracy and increasin... [more] VLD2019-66 CPSY2019-64 RECONF2019-56
pp.73-78
RECONF 2019-09-20
11:40
Fukuoka KITAKYUSHU Convention Center Accurate Pedestrian Detection in Thermal Images for FPGA
Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara (titech) RECONF2019-26
Since thermal cameras can detect the heat of objects, they can be used even if there is no light.
Therefore, object de... [more]
RECONF2019-26
pp.31-36
RECONF 2019-05-10
10:00
Tokyo Tokyo Tech Front An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2019-10
Since the convolutional neural network has a high-performance recognition accuracy,
it is expected to implement variou... [more]
RECONF2019-10
pp.49-54
HWS, VLD 2019-02-27
10:25
Okinawa Okinawa Ken Seinen Kaikan FPGA Implementation of Fully Convolutional Network for Semantic Segmentation
Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech) VLD2018-93 HWS2018-56
 [more] VLD2018-93 HWS2018-56
pp.1-6
HWS, VLD 2019-02-27
10:50
Okinawa Okinawa Ken Seinen Kaikan Spatial-Separable Convolution: Low memory CNN for FPGA
Akira Jinguji, Masayuki Shimoda, Hiroki Nakahara (titech) VLD2018-94 HWS2018-57
Object detection and image recognition using a Convolutional Neural Network (CNN) are used in embedded systems, which re... [more] VLD2018-94 HWS2018-57
pp.7-12
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
13:55
Kanagawa Raiosha, Hiyoshi Campus, Keio University Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation
Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech) VLD2018-76 CPSY2018-86 RECONF2018-50
 [more] VLD2018-76 CPSY2018-86 RECONF2018-50
pp.25-30
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-05
10:20
Hiroshima Satellite Campus Hiroshima An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-35
Since the convolutional neural network has a high-performance recognition accuracy,
it is expected to implement variou... [more]
RECONF2018-35
pp.7-12
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2018-08-01
17:00
Kumamoto Kumamoto City International Center A Deep Neuro-Fuzzy for False Negatives Reduction on an FPGA
Masayuki Shimoda, Shimpei Sato, Nakahara Hiroki (titech) CPSY2018-29
 [more] CPSY2018-29
pp.211-216
RECONF 2018-05-25
16:00
Tokyo GATE CITY OHSAKI Efficient Object Detection with Event-Driven camera and its implementation on an FPGA
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-17
We propose an object detection system using a sliding window method for an event-driven camera
which outputs a subtrac... [more]
RECONF2018-17
pp.81-86
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-18
09:40
Kanagawa Raiosha, Hiyoshi Campus, Keio University All Binarized Conventional Neural Network and its Implementation on an FPGA -- FPT2017 Design Competition Report --
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) VLD2017-63 CPSY2017-107 RECONF2017-51
 [more] VLD2017-63 CPSY2017-107 RECONF2017-51
pp.7-11
RECONF 2017-09-26
10:00
Tokyo DWANGO Co., Ltd. GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.) RECONF2017-31
 [more] RECONF2017-31
pp.51-56
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-27
15:45
Akita Akita Atorion-Building (Akita) Consideration of All Binarized Convolutional Neural Network
Masayuki Shimoda, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) CPSY2017-28
A pre-trained convolutional neural network (CNN) is a feed-forward computation perspective, which is widely used for the... [more] CPSY2017-28
pp.131-136
 Results 1 - 14 of 14  /   
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