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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS
(Joint)
2018-02-28
17:20
Okinawa Okinawa Seinen Kaikan Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes
Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] VLD2017-103
pp.85-90
VLD, HWS
(Joint)
2018-02-28
17:45
Okinawa Okinawa Seinen Kaikan Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage
Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104
Moore's Law has been miniaturizing integrated circuits, which
can make a lot of high performance devices such as PCs an... [more]
VLD2017-104
pp.91-96
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:15
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations
Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more]
VLD2016-49 DC2016-43
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
15:05
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions
Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-51 DC2016-45
We evaluate tolerance for soft errors of FFs on a 28/65 nm FDSOI. We fabricated three different layouts of non-redundant... [more] VLD2016-51 DC2016-45
pp.43-48
 Results 1 - 4 of 4  /   
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