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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, ITE-IST 2013-07-04
10:55		 Hokkaido San Refre Hakodate [Invited Talk] 32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida (Fujitsu Lab. Ltd.), Hiroki Miyaoka (FSL), Masanori Hoshino (FMSL), Yoichi Koyanagi (Fujitsu Lab. Ltd.), Takuji Yamamoto (FLA), Sanroku Tsukamoto, Hirotaka Tamura (Fujitsu Lab. Ltd.) ICD2013-27		 We present a 32Gb/s data-interpolator receiver for electrical chip-to-chip communications. The receiver front-end is clo... [more] ICD2013-27
pp.19-24
CAS, NLP 2011-10-21
14:05		 Shizuoka Shizuoka Univ. [Invited Talk] Receiver Front-End Design for CMOS High-Speed I/O
Masaya Kibune, Hirotaka Tamura, Takuji Yamamoto (FLL) CAS2011-56 NLP2011-83		 A CMOS transceiver macro for wire-line communication is required to operate at higher data rate and to be compatible wit... [more] CAS2011-56 NLP2011-83
pp.135-140
OCS, CS
(Joint)		 2011-01-28
11:15		 Tokushima The University of Tokushima 40GbE Serial and 40G VSR Compact Optical Transceiver
Mariko Sugawara, Takatoshi Yagisawa (Fujitsu/PETRA), Naoki Kuwata (Fujitsu), Yukito Tsunoda, Satoshi Ide (Fujitsu/PETRA), Takuji Yamamoto (Fujitsu Lab.), Tadashi Ikeuchi (Fujitsu/PETRA) OCS2010-112		 (Advance abstract in Japanese is available) [more] OCS2010-112
pp.77-80
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