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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 35  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2024-03-22
09:50
Nagasaki Ikinoshima Hall
(Primary: On-site, Secondary: Online)
Integration of Vector Extension and Simultaneous Multithreading for a RISC-V Processor
Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) CPSY2023-43 DC2023-109
In vector architectures, the potential for parallel execution lies in the chaining of instruction sequences. However, a ... [more] CPSY2023-43 DC2023-109
pp.29-34
RECONF 2023-09-14
16:10
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA)
Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) RECONF2023-21
In this paper,we propose a simulation environment using Post-Implementation Simulation of Vivado to confirm functions of... [more] RECONF2023-21
pp.11-12
RECONF 2023-09-14
16:20
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Integrating RISC-V Vector Extension and SMT for Embedded AI Workloads
Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) RECONF2023-22
In this paper, we plan to implement a processor that accelerates AI workloads by integrating RISC-V vector extensions th... [more] RECONF2023-22
pp.13-14
RECONF 2023-09-14
16:40
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24
Vector processors can load lots of data and perform operations in parallel.
The Vector Register Sharing Mechanism, prop... [more]
RECONF2023-24
pp.18-19
RECONF 2023-09-15
13:25
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-29
Vector Register Sharing Mechanism is a method of data transfer by connecting some of the vector registers in the vector ... [more] RECONF2023-29
pp.40-45
RECONF 2023-09-15
13:50
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) RECONF2023-30
In recent years, hardware acceleration for HPC and AI has become a challenge due to the lack of resources and the comple... [more] RECONF2023-30
pp.46-51
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
10:55
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)
Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] VLD2022-57 RECONF2022-80
pp.7-12
RECONF 2022-06-07
14:50
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Vector Register Sharing Mechanism for Hardware Acceleration
Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2022-5
In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] RECONF2022-5
pp.26-31
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
14:50
Online Online Implementation of a RISC-V SMT Core in Virtual Engine Architecture
Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] VLD2021-57 CPSY2021-26 RECONF2021-65
pp.43-48
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
15:35
Online Online Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT) VLD2021-72 CPSY2021-41 RECONF2021-80
In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasing... [more] VLD2021-72 CPSY2021-41 RECONF2021-80
pp.132-137
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-26
13:10
Online Online Automated architecture exploration on Scala-based hardware development environment
Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) VLD2020-62 CPSY2020-45 RECONF2020-81
In recent years, reconfigurable architectures such as FPGAs have been attracting more and more attention.
Design Space... [more]
VLD2020-62 CPSY2020-45 RECONF2020-81
pp.131-136
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
16:35
Ehime Ehime Prefecture Gender Equality Center Domain Knowledge-aware Machine Learning System with Rule-based Guiding
Tomoaki Shikina, Daichi Teruya, Hironori Nakajo (TAT) CPSY2019-44
Data-driven methods in machine learning rely only on the statistical nature of the data. Therefore, its predictions coul... [more] CPSY2019-44
pp.23-28
RECONF 2019-05-09
15:20
Tokyo Tokyo Tech Front High Level Synthesis of Recursive Description in a CPU+FPGA Co-design framework based on Ruby
Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) RECONF2019-6
(To be available after the conference date) [more] RECONF2019-6
pp.29-34
RECONF 2018-05-24
15:20
Tokyo GATE CITY OHSAKI A design of autoscale mechanism using high level synthesis tool for autonomous distributed system
Daichi Teruya, Hironori Nakajo (TUAT) RECONF2018-9
Since cloud computing has become widespread for various purposes,
it is drawing attention to use FPGAs. When utilizing ... [more]
RECONF2018-9
pp.45-50
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2018-03-08
15:25
Shimane Okinoshima Bunka-Kaikan Bldg. Selecting a Rule Set of the Logical Inference System with Machine Learning
Shozo Takeoka, Tomoaki Shikina, Hironori Nakajo (TUAT) CPSY2017-142 DC2017-98
Since modern logical inference system needs a huge rule-base which is increasing more and more, search space can be red... [more] CPSY2017-142 DC2017-98
pp.197-202
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
09:15
Kanagawa Raiosha, Hiyoshi Campus, Keio University FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language
Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT) VLD2017-76 CPSY2017-120 RECONF2017-64
 [more] VLD2017-76 CPSY2017-120 RECONF2017-64
pp.83-88
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
09:40
Kanagawa Raiosha, Hiyoshi Campus, Keio University Overview of an HLS Framework Surpporting IoT/CPS Development
Daichi Teruya, Hironori Nakajo (TUAT) VLD2017-77 CPSY2017-121 RECONF2017-65
We expect reduce CPU resource consumptions by offloading
processing stream data, which are incessantly generated such a... [more]
VLD2017-77 CPSY2017-121 RECONF2017-65
pp.89-94
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
15:15
Kanagawa Raiosha, Hiyoshi Campus, Keio University Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs
Yoshio Murata, Hironori Nakajo (TUAT) VLD2017-86 CPSY2017-130 RECONF2017-74
 [more] VLD2017-86 CPSY2017-130 RECONF2017-74
pp.151-156
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
11:20
Kumamoto Kumamoto-Kenminkouryukan Parea IoT Platform using an MCU-FPGA Hybrid System and Feasibility Study of Wireless Configuration
Ryota Suzuki, Hironori Nakajo (TUAT) RECONF2017-45
An MCU (Micro Control Unit) which is used in an embedded system has been recently equipped with a communication function... [more] RECONF2017-45
pp.49-54
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-24
09:00
Kanagawa Hiyoshi Campus, Keio Univ. Overview of an HLS Framework Surpporting IoT/CPS Development
Daichi Teruya, Hironori Nakajo (TUAT) VLD2016-80 CPSY2016-116 RECONF2016-61
 [more] VLD2016-80 CPSY2016-116 RECONF2016-61
pp.61-66
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