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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 15 of 15  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-18
13:00
Kanagawa Raiosha, Hiyoshi Campus, Keio University Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs
Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) VLD2017-68 CPSY2017-112 RECONF2017-56
 [more] VLD2017-68 CPSY2017-112 RECONF2017-56
pp.37-42
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
11:20
Kumamoto Kumamoto-Kenminkouryukan Parea Considerations of Inside Structures for Approximate Multipliers
Masahiro Inoue, Kaori Tajima, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) VLD2017-29 DC2017-35
Approximate arithmetic circuits are logic circuits which do not generate accurate arithmetic results.Approximate arithme... [more] VLD2017-29 DC2017-35
pp.13-18
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
13:20
Kumamoto Kumamoto-Kenminkouryukan Parea Analysis of Data Access Locality from Redis KVS Database
Hiroyuki Baba, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) CPSY2017-46
Recently, Big Data has attracted attention as a key to improving business operations and creating new industries. In add... [more] CPSY2017-46
pp.59-62
VLD, CAS, MSS, SIP 2012-07-02
14:30
Kyoto Kyoto Research Park A Quantitative Approach of Soft Error Rate Estimation by Monte-Carlo Simulation
Ken Yano, Takanori Hayashida, Toshinori Sato (Fukuokadai) CAS2012-11 VLD2012-21 SIP2012-43 MSS2012-11
In this paper a quantitative approach of SER(Soft Error Rate) of soft error rate estimation is proposed by Monte Carlo s... [more] CAS2012-11 VLD2012-21 SIP2012-43 MSS2012-11
pp.61-66
VLD 2012-03-07
09:40
Oita B-con Plaza Design automation of highly reliable VLSI by redundancy FF replacement method
Ken Yano, Takahito Yoshiki, Takanori Hayashida, Toshinori Sato (Fukuokadai) VLD2011-133
Design automation of highly reliable VLSI using canary FF is proposed. Canary FF is used to detect timing error caused f... [more] VLD2011-133
pp.79-84
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
16:05
Fukuoka Kitakyushu Science and Research Park Insertion-Point Selection of Canary FF for Timing Error Prediction
Yuji Kunitake (Kyushu Univ.), Toshinori Sato (Fukuoka Univ.), Seiichiro Yamaguchi, Hiroto Yasuura (Kyushu Univ.)
The deep submicron semiconductor technologies increase parameter ariations. The increase in parameter variations require... [more] VLD2008-74 DC2008-42
pp.85-89
ICD, IPSJ-ARC 2008-05-14
16:00
Tokyo   Considering Performance and Area Overhead in DVS System Utilizing Input Variations
Yuji Kunitake (Kyushu U.), Toshinori Sato (Fukuoka U.), Hiroto Yasuura (Kyushu U.)
The deep submicron semiconductor technologies increase parameter variations and thus the processor design becomes more d... [more] ICD2008-34
pp.93-98
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-27
08:45
Kagoshima   An Adaptive Multi-Performance Processor and its Evaluation
Seiichiro Yamaguchi, Yuichiro Oyama (Kyushu Univ.), Yuji Kunitake (Kyushu Inst. of Tech.), Tadayuki Matsumura, Yuriko Ishitobi, Masaki Yamaguchi, Donghoon Lee, Yusuke Kaneda (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst. of Tech.), Masanori Muroyama, Tohru Ishihara, Toshinori Sato (Kyushu Univ.) DC2007-84 CPSY2007-80
This paper presents an energy efficient processor which can be used as a design alternative for the dynamic voltage scal... [more] DC2007-84 CPSY2007-80
pp.1-6
CPSY 2007-10-26
09:40
Kumamoto Kumamoto University Performance, Power, and Dependability Trade-off on Multiple Clusterd Core Processors
Toshinori Sato (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst Tech) CPSY2007-31
As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A na&#23... [more] CPSY2007-31
pp.39-44
ICD, IPSJ-ARC 2007-05-31
16:15
Kanagawa   Improving Energy-efficiency of Canary-based DVS system
Toshinori Sato (Kyushu Univ), Yuji Kunitake (Kyushu Inst Tech)
In deep submicron technologies, parameter variations have become a serious problem on LSI design. We proposed canary fli... [more] ICD2007-24
pp.43-48
CPSY 2006-12-15
16:40
Tokyo Tokyo Univ. Komaba Research Campus Utilizing Data Compression to Improve Cache Performance in Multicore Processors with Dedicated Caches
Yoshitaka Ito, Akihiro Chiyonobu (KIT), Toshinori Sato (Kyushu U.)
 [more] CPSY2006-51
pp.63-68
ICD, IPSJ-ARC 2006-06-08
14:30
Kanagawa   Physical Register Access Analysis for Temperature-Aware Microarchitecture
Toshinori Sato (Kyushu Univ.), Yuji Kunitake, Akihiro Chiyonobu (Kyushu Inst. Tech.)
While the improvements in clock frequency and transistor density have achieved the continuous increase in microprocessor... [more] ICD2006-46
pp.37-42
ICD, IPSJ-ARC 2006-06-08
15:00
Kanagawa   Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka (Kyushu Inst. Tech.), Toshinori Sato (Kyushu Univ.)
We have investigated a technique for microprocessors, which achieves both high performance and low power. Based on the o... [more] ICD2006-47
pp.43-48
CPSY 2005-12-16
14:00
Tochigi Academia Hall, Utsunomiya Univ. Exploiting Typical Delays to Boost Instruction Collapsing
Toshinori Sato, Akihiro Chiyonobu (KIT)
The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide des... [more] CPSY2005-36
pp.19-24
CPSY 2004-12-20
16:05
Tokyo Ochanomizu University Towards Zero-Performance-Loss Microarchitecture for Transient Faults Tolerance
Toshinori Sato (Kyushu Inst. Tech.)
This paper presents an approach for integrating fault-tolerance techniques into microprocessors. Smaller and smaller tra... [more] CPSY2004-60
pp.73-78
 Results 1 - 15 of 15  /   
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