| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MSS, SS | 2019-01-16 10:50 |
Okinawa | Design of distribution ratio on a multi-stage parallel production line based on an optimal velocity traffic model Toru Sano, Keiji Konishi (Osaka Pref. Univ.), Takehiro Itou, Hisaya Wakayama (NEC)  MSS2018-70 SS2018-41 |
Recently, there is a need to implement production systems which can adapt to changing demand. This report proposes a mul... [more] | MSS2018-70 SS2018-41 pp.85-90 |
|
| MSS, NLP (Joint) |
2018-03-14 14:15 |
Osaka | Design of distribution ratio on a branched production line based on an optimal velocity traffic model Toru Sano, Keiji Konishi (Osaka Pref. Univ.), Takehiro Itou, Hisaya Wakayama (NEC) MSS2017-94 |
[more] | MSS2017-94 pp.89-94 |
|
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 09:25 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2009-85 CPSY2009-67 RECONF2009-70 |
[more] | VLD2009-85 CPSY2009-67 RECONF2009-70 pp.101-106 |
| RECONF | 2009-09-17 16:05 |
Tochigi | Utsunomiya Univ. | Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.) RECONF2009-26 |
One of benefit of coarse-grained dynamically reconfigurable processor arrays (DRPAs) is its low dynamic power consump... [more] |
RECONF2009-26 pp.43-48 |
| RECONF | 2009-05-14 13:30 |
Fukui | Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) RECONF2009-2 |
Dynamically Reconfigurable Processor Array(DRPA) has been received an attention as a flexible and power efficient off-lo... [more] | RECONF2009-2 pp.7-12 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 08:40 |
Kanagawa | Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction Toru Sano, Hideharu Amano (Keio Univ) VLD2008-91 CPSY2008-53 RECONF2008-55 |
We have developed and evaluated MuCCRA-1 and 2 in order to analyze architectural trade-off in dynamically reconfigurab... [more] |
VLD2008-91 CPSY2008-53 RECONF2008-55 pp.1-6 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 09:30 |
Kanagawa | Power Reduction of Dynamically Reconfigurable Processor using Dual-Vth Technologies Keiichiro Hirai, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) VLD2008-93 CPSY2008-55 RECONF2008-57 |
[more] | VLD2008-93 CPSY2008-55 RECONF2008-57 pp.13-17 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:35 |
Kanagawa | Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA Masaru Kato, Toru Sano, Hideharu Amano (Keio Univ) VLD2008-122 CPSY2008-84 RECONF2008-86 |
In the MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, an architecture of configurable low-power m... [more] |
VLD2008-122 CPSY2008-84 RECONF2008-86 pp.183-188 |
|
| RECONF | 2008-09-26 11:00 |
Okayama | Okayama Univ. | Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34 |
Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loadi... [more] | RECONF2008-34 pp.69-74 |
| RECONF | 2007-09-21 15:45 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Dynamic Reconfigurable Processor with direct execution mode Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio univ) RECONF2007-29 |
Multi-context dynamically reconfigurable processors require configuration data in the context memory to execute. It m... [more] |
RECONF2007-29 pp.83-88 |
| RECONF | 2007-05-18 09:00 |
Ishikawa | Kanazawa Bunka Hall | Techniques to decrease the Configuration Data Transfer Time in Dynamically Reconfigurable Processor MuCCRA Toru Sano, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ) RECONF2007-10 |
MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project aims to establish architectural techniques to devel... [more] |
RECONF2007-10 pp.55-60 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-18 13:50 |
Tokyo | Keio Univ. Hiyoshi Campus | Implementation of Dynamically Reconfigurable Processor MuCCRA Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Hiroki Matsutani, Vasutan Tunbunheng, Adepu Parimala, Takashi Nishimura, Masaru Kato, Shotaro Saito, Toru Sano, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano (Keio Univ.) |
[more] | VLD2006-101 CPSY2006-72 RECONF2006-72 pp.43-48 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-18 14:15 |
Tokyo | Keio Univ. Hiyoshi Campus | A Scheduling Algorithm for Multicast Configuration Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Hiroki Matsutani, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Toru Sano, Masaru Kato, Shotaro Saito, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano (Keio Univ.) |
[more] | VLD2006-102 CPSY2006-73 RECONF2006-73 pp.49-54 |
[Return to Top Page]