IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2013-04-11
17:30
Ibaraki Advanced Industrial Science and Technology (AIST) [Panel Discussion] Future prospects of memory solutions for smart society -- Can new nonvolatile memories replace SRAM/DRAM/Flash? --
Koji Nii (Renesas Erctronics), Tetsuo Endoh (Tohoku Univ.), Yoshikazu Katoh (Panasonic), Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (Elpida Memory), Atsushi Kawasumi (Toshiba), Toru Miwa (SanDisk) ICD2013-11
(To be available after the conference date) [more] ICD2013-11
p.53
ITE-MMS, MRIS 2009-10-09
10:25
Fukuoka FUKUOKA traffic center [Invited Talk] Low cost technology of phase change memory with low-contact-resistivity poly-Si selection diode
Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa, Toshiyuki Mine, Akio Shima, Yoshihisa Fujisaki, Hiroshi Moriya, Norikatsu Takaura, Kazuyoshi Torii (Hitachi) MR2009-26
We have fabricated the cross-point phase change memory with a selection diode made of poly-Si. The selection diode was f... [more] MR2009-26
pp.31-35
ICD, SDM 2009-07-17
12:00
Tokyo Tokyo Institute of Technology Cross-Point phase change memory with 4F2 cell size driven by low-contact resistivity poly-si diode
Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa, Toshiyuki Mine, Akio Shima, Yoshihisa Fujisaki, Hitoshi Kume, Hiroshi Moriya, Norikatsu Takaura, Kazuyoshi Torii (Hitachi) SDM2009-112 ICD2009-28
We have fabricated the cross-point phase change memory with a selection diode made of poly-Si. The selection diode was f... [more] SDM2009-112 ICD2009-28
pp.79-83
ICD 2007-04-12
11:10
Oita   [Invited Talk] A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current
Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5
An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit... [more] ICD2007-5
pp.23-28
SDM 2007-03-15
13:05
Tokyo Kikai-Shinko-Kaikan Bldg. Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories
Yuichi Matsui, Kenzo Kurotsuchi, Osamu Tonomura, Takahiro Morikawa, Masaharu Kinoshita, Yoshihisa Fujisaki, Nozomu Matsuzaki, Satoru Hanzawa, Motoyasu Terao, Norikatsu Takaura, Hiroshi Moriya, Tomio Iwasaki (Hitachi), Masahiro Moniwa, Tsuyoshi Koga (Renesas)
A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., c... [more] SDM2006-254
pp.1-6
ICD, ITE-CE 2006-01-26
10:30
Tokyo Kikai-Shinko-Kaikan Bldg. Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory
Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas)
This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, u... [more] ICD2005-206
pp.7-12
ICD, SDM 2005-08-19
13:50
Hokkaido HAKODATE KOKUSAI HOTEL A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi)
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] SDM2005-152 ICD2005-91
pp.55-60
ICD 2005-04-14
14:30
Fukuoka   [Invited Talk] Statistical Integration In Multigigabit DRAM Design
Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi)
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] ICD2005-8
pp.37-42
 Results 1 - 8 of 8  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan