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| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 09:25 |
Online | Online | FPGA Accelerator Design for Real-Time Object Detection Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba)  VLD2020-56 CPSY2020-39 RECONF2020-75 |
This paper presents a FPGA accelerator design for a real-time object detection algorithm using MASSD (Multi-Scale Attent... [more] | VLD2020-56 CPSY2020-39 RECONF2020-75 pp.96-100 |
| SDM, ICD, ITE-IST [detail] | 2017-08-02 13:00 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | [Invited Talk]
A 0.7V 12b 160MS/s 12.8fJ/conv. Calibration-free Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Fururta, Akihide Sai, Tetsuro Itakura (Toshiba) SDM2017-46 ICD2017-34 |
[more] | SDM2017-46 ICD2017-34 pp.115-116 |
| ICD, ITE-IST | 2014-07-03 10:50 |
Shimane | Izumo-shi (Shimane) | A 4-GS/s 5-bit Flash ADC with Dynamic pre-amplifier Junya Matsuno, Masanori Furuta, Tetsuro Itakura (Toshiba) ICD2014-21 |
[more] | ICD2014-21 pp.13-16 |
| ICD, ITE-IST | 2013-07-05 14:25 |
Hokkaido | San Refre Hakodate | A 1.0-V 12-bit Digitally Calibrated SAR ADC Using Hybrid DAC Technique Masanori Furuta, Hirotomo Ishii, Tomohiko Sugimoto, Toru Okawa, Masazumi Shiochi, Tetsuro Itakura (Toshiba) ICD2013-39 |
A 1.0-V, 12-bit, 80-MS/s two time-interleaved successive approximation register (SAR) ADC with 1.2-V differential full... [more] |
ICD2013-39 pp.93-96 |
| NLP, CAS | 2012-09-20 15:55 |
Kochi | Eikokuji Campus, University of Kochi | [Invited Talk]
All-Digital Background Calibration for Time-Interleaved ADC Using Pseudo Aliasing Signal Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura (Toshiba) CAS2012-37 NLP2012-63 |
A new adaptive background calibration for gain mismatches and sample-time mismatches in a Time-Interleaved Analog-to-Dig... [more] | CAS2012-37 NLP2012-63 pp.41-44 |
| CAS, CS, SIP | 2012-03-08 13:45 |
Niigata | The University of Niigata | A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique Masanori Furuta, Taichi Ogawa, Tetsuro Itakura (Toshiba) CAS2011-128 SIP2011-148 CS2011-120 |
An eight-channel time-interleaved ADC with individual reference voltage buffers is presented. Each channel consists of b... [more] | CAS2011-128 SIP2011-148 CS2011-120 pp.121-124 |
| ICD, ITE-IST | 2007-07-26 11:35 |
Hyogo | A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique Kazutaka Honda, Zheng Liu, Masanori Furuta, Shoji Kawahito (Shizuoka Univ.) ICD2007-44 |
This paper presents a low-power pipeline A/D converter (ADC) using a novel pre-charged multiplying digital-to-analog con... [more] | ICD2007-44 pp.41-46 |
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| ICD, ITE-IST | 2006-07-27 11:00 |
Shizuoka | 1 A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques Kazutaka Honda, Masanori Furuta, Shoji Kawahito (Shizuoka Univ.) |
This paper describes a low power low distortion pipeline ADC with 1.0V supply voltage. A 10b 100MSample/s A/D converte... [more] |
ICD2006-62 pp.11-16 |
|
| ICD, ITE-IST | 2006-07-28 14:30 |
Shizuoka | A 3500fps High-speed CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converter Masanori Furuta (Shizuoka Univ.), Toru Inoue (Photoron), Yukinari Nishikawa, Shoji Kawahito (Shizuoka Univ.) |
This paper presents a high-speed, high-sensitivity 512 x 512 CMOS image sensor with column parallel cyclic 12b ADC's and... [more] | ICD2006-74 pp.79-83 |
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| ICD, ITE-IST | 2006-07-28 16:40 |
Shizuoka | Simultaneous Calibration of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits Zheng Liu, Masanori Furuta, Shoji Kawahito (Shizuoka Univ.) |
[more] | ICD2006-78 pp.101-106 |
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