Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 14:50 |
Fukuoka |
Kyushu University |
A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-60 DC2010-27 |
As the advance in semiconductor technology, the issue of soft errors, which are transient glitches caused by particle st... [more] |
VLD2010-60 DC2010-27 pp.25-30 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 16:25 |
Fukuoka |
Kyushu University |
Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-63 DC2010-30 |
Built-in Self Test (BIST) is one of effective methods for testing today's very large-scale SoCs.In BIST scheme, a t... [more] |
VLD2010-63 DC2010-30 pp.43-48 |
DC |
2010-06-25 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Class of Partial Thru Testable Sequential Circuits with Multiplexers Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-9 |
Partially thru testable sequential circuits are known to be practically testable, and a condition for the testable seque... [more] |
DC2010-9 pp.7-11 |
DC |
2010-06-25 14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-10 |
[more] |
DC2010-10 pp.13-18 |
DC |
2010-02-15 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Study on Acceptable Faults in Digital Filters Takumi Miyaguchi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2009-75 |
In this paper, we propose a method for distinguishing acceptable and unacceptable faults in digital filters. Analyzing t... [more] |
DC2009-75 pp.63-68 |
IPSJ-SLDM, VLD, CPSY, RECONF [detail] |
2010-01-27 14:05 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-93 CPSY2009-75 RECONF2009-78 |
Fail-soft systems with reconfigurable devices, which recover themselves by repeating isolation of faulty portions with g... [more] |
VLD2009-93 CPSY2009-75 RECONF2009-78 pp.149-154 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 13:45 |
Kochi |
Kochi City Culture-Plaza |
A Yield Model with Testability and Repairability Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-54 DC2009-41 |
For deep-submicron technology, the increase in transitive and permanent faults of LSIs is a critical problem due to the ... [more] |
VLD2009-54 DC2009-41 pp.89-94 |
DC |
2009-06-19 11:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2009-12 |
If the existence of a fault in a circuit only causes negligible effect on its application,
the fault is said to be acce... [more] |
DC2009-12 pp.13-18 |
DC, CPSY |
2009-04-21 15:45 |
Tokyo |
Akihabara Satellite Campus, Tokyo Metropolitan Univ. |
A design of testable response analyzers in built-in self-test Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2009-7 DC2009-7 |
In the BIST(Built-in self-test) scheme, the occurrence of faults in BIST circuits, e.g., test generators and response co... [more] |
CPSY2009-7 DC2009-7 pp.37-42 |
DC |
2009-02-16 10:00 |
Tokyo |
|
On the Acceleration of Threshold Test Generation Based on Fault Acceptability Yusuke Nakashima, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) DC2008-68 |
[more] |
DC2008-68 pp.1-6 |
DC |
2008-12-12 13:25 |
Yamaguchi |
|
A Test Generation Model for Threshold Testing Kenta Sutoh, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2008-60 |
Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancemen... [more] |
DC2008-60 pp.5-10 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka |
Kitakyushu Science and Research Park |
[Poster Presentation]
A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) VLD2008-80 DC2008-48 |
In this work, we discuss a method for reducing test data by test point insertion. Focusing on the fact that test points ... [more] |
VLD2008-80 DC2008-48 pp.121-126 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka |
Kitakyushu Science and Research Park |
[Poster Presentation]
A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2008-81 DC2008-49 |
The hybrid delay scan design [1], where part of FFs can be controlled as skewed-load ones,
is an effective method for a... [more] |
VLD2008-81 DC2008-49 pp.127-132 |
DC, CPSY |
2008-04-23 11:30 |
Tokyo |
Tokyo Univ. |
A Study on Reliability and Performance of FPGA-Based Fault Tolerant Systems Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2008-4 DC2008-4 |
FPGAs (Field-Programmable Gate Arrays), which can implement arbitrary logic circuits
any number of times by loading con... [more] |
CPSY2008-4 DC2008-4 pp.19-24 |
DC |
2008-02-08 13:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Synthesis of Fault Secure Datapaths with DFG Restructuring Hirotaka Shiomichi (Hiroshima City Univ.), Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City) DC2007-75 |
This paper considers a method for synthesizing fault secure datapaths by concurrent
error detection.
Defining the comp... [more] |
DC2007-75 pp.51-56 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:55 |
Fukuoka |
Kitakyushu International Conference Center |
An optimization of thru trees for test generation based on acyclical testability Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2007-72 DC2007-27 |
The class of acyclic sequential circuits is $\tau^2$-bounded, i.e., acyclic sequential circuits are practically easily t... [more] |
VLD2007-72 DC2007-27 pp.13-18 |