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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2023-09-15 14:15 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Library Development for RISC-V FPGA SoCs Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)  RECONF2023-31 |
[more] | RECONF2023-31 pp.52-57 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-04 18:20 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25 |
In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] | CPSY2023-25 DC2023-25 pp.100-105 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 13:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] | CPSY2022-8 DC2022-8 pp.41-46 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-15 15:20 |
Ehime | Ehime Prefecture Gender Equality Center | Evaluation of Inter-chip Inductive Coupling Wireless Communication Technology Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano (Keio Univ.) CPSY2019-48 |
Building block computing systems, which is one of the three-dimensional stacked LSI systems, use a wireless communicatio... [more] | CPSY2019-48 pp.59-64 |
| ICD, CPSY, CAS | 2018-12-23 14:15 |
Okinawa | Sayaka Terashima, Takuya Kojima, Kazusa Musha, Hayate Okuhara, Hideharu Amano (Keio Univ.) CAS2018-110 ICD2018-94 CPSY2018-76 |
(To be available after the conference date) [more] | CAS2018-110 ICD2018-94 CPSY2018-76 pp.125-130 |
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| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 15:15 |
Hiroshima | Satellite Campus Hiroshima | Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Hideharu Amano (Keio Univ.) CPSY2018-42 |
A building block computing system is one of the promising 3D Stacked VLSIs. It adopts an inductive coupling ThruChip Int... [more] | CPSY2018-42 pp.53-58 |
| CPSY | 2018-11-27 15:30 |
Gifu | Hida Area Local Industry Promotion Center | [Technology Exhibit]
Low Power Stream Processing on a Variable Pipelined Accelerator CCSOTB2 Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Ng. Doan Anh Vu, Hideharu Amano (Keio Univ.) CPSY2018-33 |
[more] | CPSY2018-33 pp.1-5 |
| RECONF | 2018-09-18 14:10 |
Fukuoka | LINE Fukuoka Cafe Space | Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan, Hideharu Amano (Keio Univ.) RECONF2018-31 |
[more] | RECONF2018-31 pp.67-72 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2018-03-07 18:10 |
Shimane | Okinoshima Bunka-Kaikan Bldg. | Design and Implementation of A Critical Path Monitor for Adaptive Voltage Scaling Ryosuke Kazami, Hayate Okuhara, Hideharu Amano (Keio Univ.) CPSY2017-139 DC2017-95 |
(To be available after the conference date) [more] | CPSY2017-139 DC2017-95 pp.125-130 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A shared memory chip for twin-tower of chips Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Hideharu Amano (Keio Univ.) VLD2017-34 DC2017-40 |
A shared memory chip for the building-block computing system using ThruChip Interface (TCI) is developed and evaluated.T... [more] | VLD2017-34 DC2017-40 pp.43-48 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | RECONF2017-41 |
(To be available after the conference date) [more] | RECONF2017-41 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 13:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Real chip evaluation of a low-power overhead body bias controller Hayate Okuhara, Akram BenAhmed, Hideharu Amano (Keio Univ.) CPM2017-81 ICD2017-40 IE2017-66 |
[more] | CPM2017-81 ICD2017-40 IE2017-66 pp.9-14 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-23 10:55 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | Power Optimization for Pipelined CGRA with Intger Linear Program Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng.Doan Anh Vu, Hideharu Amano (Keio Univ.) RECONF2017-16 |
(To be available after the conference date) [more] | RECONF2017-16 pp.81-86 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-09 16:10 |
Okinawa | Kumejima Island | Power Reduction for Pipelined CGRA with the Controlling Variable Pipeline and the Body Bias Voltage Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) CPSY2016-140 DC2016-86 |
(To be available after the conference date) [more] | CPSY2016-140 DC2016-86 pp.51-56 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 09:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | VLD2016-94 CPSY2016-130 RECONF2016-75 |
(To be available after the conference date) [more] | VLD2016-94 CPSY2016-130 RECONF2016-75 pp.159-164 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:40 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Variable Pipeline Ultra Low-power Coarse Grained Reconfigurable Accelelator Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano (Keio Univ.) RECONF2016-41 |
[more] | RECONF2016-41 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Development and evaluation of on-chip body bias tuning scheme Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano (Keio Univ.) CPSY2016-54 |
[more] | CPSY2016-54 pp.35-40 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | CPSY2016-55 |
[more] | CPSY2016-55 pp.41-46 |
| RECONF | 2016-05-19 16:55 |
Kanagawa | FUJITSU LAB. | Fine-grained body bias control to minimize leakage current of CGRA Hayate Okuhara, Johannes Maximilian Kuehn, Akram Ben Ahmed, Hideharu Amano (Keio Univ.) RECONF2016-15 |
[more] | RECONF2016-15 pp.71-76 |
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