IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2012-08-03
13:10		 Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A Fast-Transient-Response Digital Low-Dropout Regulator Comprising Thin-Oxide MOS Transistors in 40-nm CMOS process
Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita (Renesas Electronics), Koichiro Ishibashi (Univ. of Electro-Comm.), Kazumasa Yanagisawa (Renesas Electronics) SDM2012-82 ICD2012-50		 A digital low-dropout (LDO) regulator comprising only thin-oxide MOS transistors was developed. The input voltage to the... [more] SDM2012-82 ICD2012-50
pp.105-110
VLD, IPSJ-SLDM 2010-05-20
13:05		 Fukuoka Kitakyushu International Conference Center A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control
Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) VLD2010-7		 A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transit... [more] VLD2010-7
pp.67-72
MSS 2010-01-21
13:25		 Aichi Toyota Central R&D Labs. Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme
Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38		 We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] CST2009-38
pp.7-12
ICD, SDM 2007-08-23
09:20		 Hokkaido Kitami Institute of Technology Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding
Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71		 This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] SDM2007-143 ICD2007-71
pp.11-16
 Results 1 - 4 of 4  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan